Workshop della Commissione Calcolo e Reti dell'INFN - 2015 (LNF)

25 May 2015, 09:00 → 29 May 2015, 15:00 Europe/Rome

Aula Touschek (Laboratori Nazionali di Frascati dell'INFN)

Claudio Grandi (BO), Dario Livio Menasce (MIB)

Il Workshop si terrà dal 25 al 29 maggio 2015, nella Sala Touchek dei Laboratori Nazionali di Frascati dell'INFN. Avrà inizio alle ore 14.00 di lunedi' 25 maggio e terminera' alle ore 13.00 circa di venerdi' 29 maggio.

Slides

• IMG_9552_foto_di_gruppo.jpg
• Termini_TorVergata.pdf
• TorVergata-Termini.pdf

Monday, 25 May

09:00 → 12:30 Riunione interna del Sistema Informativo

Convener: Marco Serra (ROMA1)

slides ws_ccr_052015.pptx

12:30 → 14:00 Registrazione al Workshop

14:00 → 14:20 Apertura dei lavori e saluto del Direttore dei LNF

14:20 → 15:00 Comunicazioni

Speakers: Claudio Grandi (BO), Dario Livio Menasce (MIB)

Slides 20150525-apertura-WS-CCR.pptx

15:00 → 15:30 Relazione Direttore Generale

Speaker: Luigi Giunti (AC)

15:30 → 19:00 Il Sistema Informativo e l'infrastruttura di autenticazione e autorizzazione dell'INFN

Conveners: Dr Enrico Maria Fasanelli (LE), Marco Serra (ROMA1)

15:30 Strumenti e sviluppi SI per Area Ricerca

20' + 10' di discussione

Speaker: Dr Antonello Paoletti (AC)

Slides CCR_SISINFO_mag2015.pdf CCR_SISINFO_mag2015.ppt

16:00 Strumenti SI per la dematerializzazione

20' + 10' di discussione

Speaker: Stefano Longo (CNAF)

Slides Slides.pdf

16:30 Strumenti e sviluppi SI per Area del Personale

20' + 10' di discussione

Speaker: Francesco Serafini (AC)

Slides presentazione_ccr2015_area_personale.pptx

17:00 Pausa caffè

17:30 Stato di INFN-AAI e suo utilizzo nelle strutture

Speaker: Dael Maselli (LNF)

Slides AAI_-_stato_infrastruttura_2015.pdf

17:50 Sviluppi "in cantiere"

Speaker: Francesco Serafini (AC)

Slides ccr2015_serafini_aai.pptx

18:00 Tavola rotonda sul futuro di AAI

- Attualità di INFN-AAI: • l'architettura è ancora attuale? • cosa possono fare i servizi di calcolo con l'attuale implementazione • cosa manca e cosa si può fare per completare i pezzi mancanti - Sostenibilità di INFN-AAI

Slides Tavola_Rotonda_AAI.pdf

Tuesday, 26 May

09:00 → 13:30 Cloud Computing

Conveners: Davide Salomoni (CNAF), Doina Cristina Aiftimiei (PD), Stefano Bagnasco (TO), Stefano Longo (CNAF), Stefano Stalio (LNGS)

09:00 Use cases, architecture and roadmap for the INFN Corporate Cloud

Speaker: Stefano Stalio (LNGS)

Slides wscr201505.pdf

09:20 Il progetto EGI-Engage: un percorso verso la cloud

Speaker: Luciano Gaido (TO)

Slides EGI-Engage-CCRWS-26052015.pptx

09:40 RMLab: Un approccio innovativo al datacenter distribuito.

Speaker: Federico Zani (ROMA2)

Slides https://docs.google.com/presentation/d/1rl_E9YPzR57cdrjeItpIz9Ta1DV5n6PD8-DCayxTgRM/edit?usp=sharing

10:00 INDIGO e la Cloud INFN

Speaker: Davide Salomoni (CNAF)

Slides 20150526_ds_indigo.pdf

10:20 Cloud dell'Area Padovana: status update

Speaker: Alvise Dorigo (PD)

Slides CCR_2015.pdf

10:40 Discussione

11:00 Pausa caffè

11:30 Cloud@CNAF - the long road to Juno

Speaker: Matteo Panella (CNAF)

Slides cloud_cnaf_long_road_to_juno_v1.0.pdf cloud_cnaf_long_road_to_juno_v1.0.pptx

11:50 Elastic Extension of CMS Computing Centre Resources on External Clouds

Speaker: Giuseppe Codispoti (B)

Slides BolognaT3-cloud_bursting_v1.pdf

12:10 Dynamic partitioning per multicore/himem e per cloud

Speaker: Dr Stefano Dal Pra (CNAF)

Slides Dynpart_per_mcore_cloud.pdf

12:30 Report da OpenStack Summit

Speaker: Giuseppe Andronico (CT)

Slides Report da OpenStack Summit

12:50 T2 virtuale su OpenStack

Speaker: Mr Giuseppe Platania (CT)

Slides ALICE-T2-CT.pdf

13:10 Discussione

13:30 → 14:45 Pausa pranzo

14:45 → 19:00 Stato e prospettive del calcolo negli esperimenti (I)

Conveners: Dr Alberto Garfagnini (PD), Gianpaolo Carlino (NA), Rosario Turrisi (INFN-PD)

14:45 Infrastruttura Torino

Speaker: Dr Sara Vallero (TO)

Slides InfraTorino.pdf

15:35 discussione

15:40 Calcolo di Belle II

Speaker: Dr Vania Boccia (INFN-Na)

Slides Calcolo_di_Belle2_-_VBoccia_-_CCR.pdf Calcolo_di_Belle2_-_VBoccia_-_CCR.pptx

16:05 discussione

16:10 Introduzione su CSN2

Speaker: Dr Alberto Garfagnini (PD)

Slides gr2_calcolo.pdf

16:30 Il modello di calcolo di JUNO

Speaker: Dr Alberto Garfagnini (PD)

Slides juno_computing_model.pdf

16:45 discussione

17:00 Pausa caffè

17:30 Il modello di Calcolo di CTA

Speaker: Domenico D'Urso (ROMA2)

Slides modello_calcolo_CTA_durso.pdf

17:50 Il calcolo di VIRGO

Speaker: Gergely Debreczeni

Slides Gergely_VIRGO.pdf

18:10 discussione

18:15 Il calcolo per KM3NET

Speaker: Pasquale Migliozzi (NA)

Slides Migliozzi.pptx

18:35 discussione

Wednesday, 27 May

09:00 → 13:00 Stato e prospettive del calcolo negli esperimenti (II) ed evoluzione dell’infrastruttura

Conveners: Dr Alberto Garfagnini (PD), Donatella Lucchesi (PD), Gaetano Maron (LNL), Gianpaolo Carlino (NA), Laura Perini (MI), Rosario Turrisi (INFN-PD)

09:00 Il calcolo scientifico di JLAB12

Speaker: Mikhail Osipenko (GE)

09:20 Il calcolo in AGATA

Speaker: Dino Bazzacco (PD)

09:40 discussione

09:50 Il calcolo a LHC (ALICE, ATLAS, CMS, LHCb)

Speaker: Dario Barberis (GE)

Slides Barberis-LHC_computing-2015.pdf

10:25 discussione

10:30 Coffee break

11:00 Tier1: stato e prospettive

Speaker: Luca Dell'Agnello (CNAF)

Slides ccr20150527.pdf

11:20 Stato e Prospettive dell'infrastruttura di rete

Speaker: Dr Massimo Carboni (LNF)

Slides 2015-05-27_CCR-INFN-GARR_Evolution-v4.pdf

11:50 discussione

12:00 EU-T0_It

Speaker: Donatella Lucchesi (PD)

Slides EU_T0-CCR2015.pdf

12:20 discussione

12:30 Multimessenger

Speaker: Gianluca Gemme (GE)

Slides Infrastrutture_di_calcolo_per_la_fisica_astroparticellare.pdf

12:50 discussione

13:00 → 13:30 Presentazione DELL: "Something is Changing in the Storage Panorama"

Le nuove tecniche di riduzione del wear-out delle memorie a stato solido e il raggiungimento del limite fisico di densità delle tecnologie di memorizzazione magnetica tradizionale PMR saranno alla base del prossimo cambio di paradigma nella gestione del layer di storage dei sistemi di calcolo. Scopo dell’intervento è fare una panoramica sullo stato dell’arte e sulle previsioni di evoluzione a medio e lungo termine delle tecnologie di memorizzazione magnetica, nonché illustrare le nuove tecnologie di miglioramento dell’endurance dei dischi a stato solido, correlandole al dimensionamento di aree storage basate su SSD.

Slides Dell@CCR2015_Workshop_public.pdf

13:30 → 14:45 Pausa pranzo

14:45 → 18:45 Nuove tecnologie hardware

Conveners: Daniele Cesini (CNAF), Michele Michelotto (PD), Piero Vicini (ROMA1)

14:45 Introduction

Speakers: Michele Michelotto (PD), Piero Vicini (ROMA1)

14:55 The INFN COSA project

COSA (COmputing on SoC Architectures) is an CSN5 2 years (2015-2016) project aimed at evaluating the potential, the performances and the running costs of computing systems based on low power System-on-Chip (SoC). A cluster of development boards based on SoCs will be installed and configured. It will dimensioned to run in a realistic way (i.e. for real life use cases) scientific applications taken from the theoretical and experimental physics realms. The cluster will be open to INFN users interested in testing and acquiring expertise in the porting of parallel applications to low-power systems. The COSA cluster will run real parallel applications, computationally intensive, interesting for the INFN and eventually for other scientific communities collaborating with the INFN. The investigation of the interconnections among the SoCs will be another relevant part of the project. In this perspective, the project foresees the creation of a second cluster in ROME devoted to the study and eventually the design of appropriate network solutions. This cluster will not be open to users and will be based on FPGA technologies.

Speaker: Daniele Cesini (CNAF)

Slides cosa_CCR_270515_cesini.pdf cosa_CCR_270515_cesini.pptx

15:25 Energy vs time performances of HPC applications on Tegra K1

Energy efficiency is lately becoming of paramount importance in the HPC field and high-end processors are quickly evolving towards more advanced power-saving and power-monitoring technologies. On the other hand, low-power processors, designed for the mobile market, are gaining interest in the HPC area thanks to their increasing computing capabilities, in conjunction with their competitive pricing and low power consumption. In this work we explore energy and computational performances of a Tegra K1 mobile processor, in the context of HPC, using a Lattice Boltzmann application as a benchmark. Current drawing of the board is monitored with custom hardware for different CPU, GPU and memory clocks.

Speaker: Enrico Calore (FE)

Slides time-energy-jetson.pdf

15:55 Triggering Events with GPUs at ATLAS

The growing complexity of events produced in LHC collisions demands more and more computing power both for the on line selection and for the offline reconstruction of events. In recent years, the explosive performance growth of massively parallel processors like Graphical Processing Units both in computing power and in low energy consumption, make GPU extremely attractive for using them in a complex high energy experiment like ATLAS. Together with the optimization of reconstruction algorithms exploiting this new massively parallel paradigm, a small scale prototype of the full ATLAS High Level Trigger exploiting GPU has been implemented. We discuss the integration procedure of this prototype, the achieved performance and the prospects for the future.

Speaker: Lorenzo Rinaldi (BO)

Slides rinaldi-gpu-ccr15.pptx

16:15 Event building for the LHCb Upgrade

During the LHC Run 1 the LHCb experiment has successfully performed a large number of world-class precision measurements in heavy flavour physics by having collected over 3 fb-1 at centre-of-mass energies of 7 TeV and 8TeV. However, even after an additional expected integrated luminosity of 5-6 fb-1 in Run 2, many of the LHCb measurements will remain limited by statistics. The current 1 MHz readout system is the main bottle neck to run LHCb at higher luminosity and with higher trigger efficiencies. LHCb will therefore undergo a major upgrade in the Long Shutdown 2 of LHC (2018- 2019) aimed at collecting an order of magnitude more data by 2028. The upgrade consists of a new full readout at the LHC bunch crossing rate (40 MHz) with the ultimate flexibility of only a software trigger. In order to increase the instantaneous luminosity five times, up to 2x10^33 cm-2s-1, several sub-detector upgrades are also underway, such to cope with the expected higher occupancies and radiation dose. The talk will focus on the PCIe based readout and the Event Builder we are developing in collaboration of INFN Bologna, INFN-CNAF and the LHCb Online CERN group.

Speaker: Domenico Galli (BO)

Slides galli-2015-05-27.pdf galli-2015-05-27.pptx

16:45 Pausa caffè

17:15 NaNet: a Family of FPGA-based Network Interface Cards for Real-Time Trigger and Data Acquisition Systems in HEP Experiments.

NaNet is a modular design of a family of FPGA-based PCIe Network Interface Cards specialized for low-latency real-time operations. NaNet features a Network Interface module that implements RDMA-style communications both with the host (CPU) and the GPU accelerators memories (GPUDirect RDMA) relying on the services of a high performance PCIe Gen2/3 x8 core. NaNet I/O Interface is highly flexible and is designed for low and predictable communication latency: a dedicated stage manages the network stack protocol in the FPGA logic offloading the host operating system from this task and thus eliminating the associated process jitter effects. Between the two above mentioned modules, stand the data processing and switch modules: the first implements application-dependent processing on streams, e.g. performing compression algorithms, while the second routes data streams between the I/O channels and the Network Interface module. This general architecture has been specialized up to now into three configurations, namely NaNet-1, NaNet3and NaNet-10 in order to meet the requirements of different experimental setups. NaNet-1 features a GbE channel plus three custom 20 Gbps serial channels, NaNet3 supports four custom 2.5 Gbps deterministic latency optical channels while NaNet-10 features four 10GbE SFP+ ports.We will provide performance results for the three NaNet implementations and describe their usage in the CERN NA62 and KM3NeT-IT underwater neutrino telescope experiments, showing that the architecture is very flexible and yet capable of matching the requirements of low-latency real-time applications with intensive I/O tasks involving the CPU and/or the GPU accelerators.

Speaker: Alessandro Lonardo (ROMA1)

Slides NaNetCCR20150527.pdf

17:45 INFN H2020 projects for new hardware technologies

Speaker: Piero Vicini (ROMA1)

Slides PV_ccr_maggio_2015.pdf

18:15 Some experiences with Power Efficient Architectures in HEP

Speaker: Mr Felice Pantaleo (CERN)

Slides pantaleo_SoC_CCR_2015.pptx

20:00 → 23:00 Cena sociale

Thursday, 28 May

09:00 → 13:00 Nuove tecnologie Software

Conveners: Dario Livio Menasce (MIB), Dr Francesco Giacomini (CNAF), Roberto Alfieri (PR)

09:00 Perspective for parallel computing in a close and far future

Talk comprensivo di tutti gli esperimenti LHC

Speaker: Mr Felice Pantaleo (CERN)

Slides pantaleo_sw_overview_ccr_frascati_15.pptx

10:00 New software technologies: brains and hands

Speaker: Maria Pia (GE)

Slides brainshands.pdf

10:30 Experience with software quality metrics: two or three case studies

Speaker: Elisabetta Ronchieri (INFN CNAF)

Slides WorkshopCCRRonchieri.pdf

10:50 Pausa caffè

11:10 Exascale: challenges and opportunities in a power constrained world

The top500 list of last November shows for the first time a clear sign of slow down in the growing rate of supercomputers power. Not only just one new system enter in the top10 (wrt June 2014), but also the last system of the top500 display very little performance improvement. It is not a mistary that the long standing Moore's low is approaching an inevitable decline. Two factors mostly contribute to this trend: little improvement in silicon chips and power constraints. For many datacenters the capacity in term of electrical power is coming to its limit, and without a dramatic improvement in computing efficiency this limit determine the maximum size of the high-end system that can be deployed. To make Exascale a reality by the ends of the decade dramatic changes in datacenters, architectures and in particular software paradigm need to be faced. In this talk the challenges and opportunities related to these changes will be discussed and confronted with the roadmap to exascale systems.

Speaker: Dr Carlo Cavazzoni (CINECA)

Slides Frascati_Maggio2015_Cavazzoni.pptx

11:40 Portability, Efficiency and Maintainability: the case of OpenACC

An increasing number of HPC systems adopt heterogeneous node architectures, combining traditional multi-core CPUs with energy-efficient massively parallel accelerators, such as GPUs. The need to exploit the computing power of these systems, in conjunction with the lack of standardization in their hardware and/or programming frameworks, raises new issues with respect to scientific software development choices, which strongly impact software maintainability, portability and performance. Several new programming environments have been introduced recently, in order to address these issues. In particular, the OpenACC programming standard has been designed to ease the software development process for codes targeted for heterogeneous machines, helping to achieve code and performance portability. In this talk we present the OpenACC language as a tool to design, port and optimize codes intended to be portable across present and future heterogeneous HPC architectures.

Speaker: Dr Enrico Calore (INFN, Sezione di Ferrara)

Slides openacc-hpc.pdf

12:10 Quale licenza per il software INFN?

Speaker: Dr Francesco Giacomini (CNAF)

Slides licenza_software.pdf

12:40 Rapporto sullo stato di HSF (dopo CHEP2015)

Speaker: Dario Livio Menasce (MIB)

Slides HSFPresentaionCCR.pptx

13:00 → 13:30 Presentazione SUPERMICRO: "Attuali trend nello sviluppo di tecnologie e componenti hardware a supporto delle esigenze di HPC"

Obiettivo della presentazione è quello di fare il punto su quali tecnologie e relativi componenti hardware di recente introduzione nelle architetture dei server possono favorire e migliorare le prestazioni degli stessi per un loro migliore utilizzo in ambito HPC. In particolare si tratteranno argomenti in ambito SSD, RAM e Coprocessori. Inoltre verranno presentati le linee di sistemi Supermicro che già offrono al loro interno l’utilizzo di queste tecnologie e componenti.

Speaker: Luca Arduini (SUPERMICRO)

Slides Supermicro_Trends_in_Technologyv2.pptx

13:30 → 14:45 Pausa pranzo

14:45 → 18:45 Attività dei gruppi di lavoro della CCR

Conveners: Luca Giovanni Carbone (MIB), Michele Michelotto (PD), Dr Paolo Lo Re (NA), Sandra Parlati (LNGS)

14:45 Condor: stato e prospettive

Speaker: Francesco Piero Lorenzo Prelz (MI)

Slides http://www.mi.infn.it/~prelz/condor-update-2015/

15:15 Security: scansioni di primavera e altro

Speaker: Roberto Cecchini (FI)

Slides Riduzione_del_perimetro.pdf Sicurezza_WS_150529.pdf

15:45 Mailing: tavola rotonda

PEC

Speaker: Alessandro Brunengo (GE)

Slides Presentazione.pdf

16:35 DNS HA per Cloud INFN-CC

Speaker: Stefano Longo (CNAF)

Slides Slide.pdf

16:45 Pausa caffè

17:15 !CHAOS: a Cloud of Controls

!CHAOS è un framework dedicato al controllo, monitoraggio, acquisizione e archiviazione dati di sensori e sottosistemi complessi. L'obiettivo di !CHAOS è di studiare e implementare un prototipo di Control as a Service. Nella presentazione verrano descritte le problematiche infrastrutturali, le soluzioni tecnologiche utilizzate per garantire la massima scalabilità in ottica di un deployment in ambiente cloud.

Speakers: Michele Antonio Tota (LNF), Ramon Orrù (LNF)

Slides chaos@CCR.pptx

Friday, 29 May

09:00 → 12:30 Attività dei gruppi di lavoro della CCR

Conveners: Luca Giovanni Carbone (MIB), Michele Michelotto (PD), Dr Paolo Lo Re (NA), Sandra Parlati (LNGS)

09:00 CEPH come soluzione di storage consolidation

Verrà presentata l’attività svolta a Bari su CEPH sia come backend per i componenti dell’infrastruttura cloud sia come soluzione di storage per la farm. Verranno riportati i risultati ottenuti in termini di performance, stabilità operativa, flessibilità e semplicità di gestione. Verranno anche descritte le configurazioni adottate che permettono di implementare il tiering dello storage consentendo il caching automatico dei dati maggiormente utilizzati e il supporto QoS del Block Storage.Si descriveranno anche i metodi studiati per il deployment e la configurazione automatica di Ceph: in particolare di Puppet scelto come tool unico per gestire sia la farm sia l’infrastruttura cloud.

Speaker: Marica Antonacci (BA)

Slides Ceph-CCR-Frascati-29052015.pdf

09:30 Studio di un sistema di e-voting per l'INFN

La presentazione ha lo scopo di introdurre il lavoro preliminare svolto nella definizione di un sistema di e-voting per utilizzo interno da parte dell'INFN. Vengono brevemente discusse la fase di analisi dei requisiti e la valutazione delle soluzioni già esistenti che verranno utilizzate come base per l'implementazione successiva. Vengono inoltre individuate le attività di sviluppo software necessarie a garantire le caratteristiche richieste.

Speaker: Ramon Orrù (LNF)

Slides

• evoting_-_light.pptx
• https://docs.google.com/presentation/d/1ZIEzaRzAJWExevPIx5PNnVeP9nTBSaWNYkzS0rllWBE/edit?usp=sharing
• https://docs.google.com/presentation/d/1zXiQjjbw-9GY1Dto-GCg-dzsVSYGnMyR_TeOSVb0_-M/edit?usp=sharing

10:00 Network: SDN

Speaker: Lorenzo Chiarelli (GARR/CNAF)

Slides Software_Defined_Networks@CCR2015.pdf

10:20 Network: Infrastrutture virtuali

Speaker: Dr Massimo Carboni (LNF)

Slides 2015-05-29_pres-infr-virtuali-v4.pdf

10:40 Tavola rotonda su Firewall e sicurezza di rete

Speaker: Stefano Zani (CNAF)

Slides 2015-05-29_Firewall-Tavola-Rotonda.pptx

11:30 Pausa caffè

12:00 Connettività wireless: varie ed eventuali

Speakers: Massimo Pistoni (LNF), Riccardo Veraldi (CNAF)

Slides WiFi-INFN-wsccr15.pptx

12:30 → 13:00 Chiusura dei lavori

Speakers: Claudio Grandi (BO), Dario Livio Menasce (MIB)