Workshop della Commissione Calcolo e Reti dell'INFN - 2015 (LNF)
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Europe/Rome
Aula Touschek (Laboratori Nazionali di Frascati dell'INFN)
Aula Touschek
Laboratori Nazionali di Frascati dell'INFN
Via E. Fermi, 40 00044 Frascati (Roma)
Claudio Grandi
(BO),
Dario Livio Menasce
(MIB)
Description
Il Workshop si terrà dal 25 al 29 maggio 2015, nella Sala Touchek dei Laboratori Nazionali di Frascati dell'INFN. Avrà inizio alle ore 14.00 di lunedi' 25 maggio e terminera' alle ore 13.00 circa di venerdi' 29 maggio.
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Participants
146
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- 09:00 → 12:30
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12:30
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14:00
Registrazione al Workshop 1h 30m
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14:00
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14:20
Apertura dei lavori e saluto del Direttore dei LNF 20m
- 14:20 → 15:00
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15:00
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15:30
Relazione Direttore Generale 30mSpeaker: Luigi Giunti (AC)
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15:30
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19:00
Il Sistema Informativo e l'infrastruttura di autenticazione e autorizzazione dell'INFNConveners: Dr Enrico Maria Fasanelli (LE), Marco Serra (ROMA1)
- 15:30
- 16:00
- 16:30
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17:00
Pausa caffè 30m
- 17:30
- 17:50
- 18:00
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09:00
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13:30
Cloud ComputingConveners: Davide Salomoni (CNAF), Doina Cristina Aiftimiei (PD), Stefano Bagnasco (TO), Stefano Longo (CNAF), Stefano Stalio (LNGS)
- 09:00
- 09:20
- 09:40
- 10:00
- 10:20
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10:40
Discussione 20m
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11:00
Pausa caffè 30m
- 11:30
- 11:50
- 12:10
- 12:30
- 12:50
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13:10
Discussione 20m
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13:30
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14:45
Pausa pranzo 1h 15m
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14:45
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19:00
Stato e prospettive del calcolo negli esperimenti (I)Conveners: Dr Alberto Garfagnini (PD), Gianpaolo Carlino (NA), Rosario Turrisi (INFN-PD)
- 14:45
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15:35
discussione 5m
- 15:40
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16:05
discussione 5m
- 16:10
- 16:30
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16:45
discussione 5m
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17:00
Pausa caffè 30m
- 17:30
- 17:50
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18:10
discussione 5m
- 18:15
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18:35
discussione 5m
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09:00
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13:30
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09:00
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13:00
Stato e prospettive del calcolo negli esperimenti (II) ed evoluzione dell’infrastrutturaConveners: Dr Alberto Garfagnini (PD), Donatella Lucchesi (PD), Gaetano Maron (LNL), Gianpaolo Carlino (NA), Laura Perini (MI), Rosario Turrisi (INFN-PD)
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09:00
Il calcolo scientifico di JLAB12 20mSpeaker: Mikhail Osipenko (GE)
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09:20
Il calcolo in AGATA 20mSpeaker: Dino Bazzacco (PD)
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09:40
discussione 10m
- 09:50
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10:25
discussione 5m
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10:30
Coffee break 30m
- 11:00
- 11:20
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11:50
discussione 10m
- 12:00
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12:20
discussione 10m
- 12:30
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12:50
discussione 10m
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09:00
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13:00
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13:30
Presentazione DELL: "Something is Changing in the Storage Panorama" 30mLe nuove tecniche di riduzione del wear-out delle memorie a stato solido e il raggiungimento del limite fisico di densità delle tecnologie di memorizzazione magnetica tradizionale PMR saranno alla base del prossimo cambio di paradigma nella gestione del layer di storage dei sistemi di calcolo. Scopo dell’intervento è fare una panoramica sullo stato dell’arte e sulle previsioni di evoluzione a medio e lungo termine delle tecnologie di memorizzazione magnetica, nonché illustrare le nuove tecnologie di miglioramento dell’endurance dei dischi a stato solido, correlandole al dimensionamento di aree storage basate su SSD.
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13:30
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14:45
Pausa pranzo 1h 15m
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14:45
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18:45
Nuove tecnologie hardwareConveners: Daniele Cesini (CNAF), Michele Michelotto (PD), Piero Vicini (ROMA1)
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14:45
Introduction 10mSpeakers: Michele Michelotto (PD), Piero Vicini (ROMA1)
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14:55
The INFN COSA project 30mCOSA (COmputing on SoC Architectures) is an CSN5 2 years (2015-2016) project aimed at evaluating the potential, the performances and the running costs of computing systems based on low power System-on-Chip (SoC). A cluster of development boards based on SoCs will be installed and configured. It will dimensioned to run in a realistic way (i.e. for real life use cases) scientific applications taken from the theoretical and experimental physics realms. The cluster will be open to INFN users interested in testing and acquiring expertise in the porting of parallel applications to low-power systems. The COSA cluster will run real parallel applications, computationally intensive, interesting for the INFN and eventually for other scientific communities collaborating with the INFN. The investigation of the interconnections among the SoCs will be another relevant part of the project. In this perspective, the project foresees the creation of a second cluster in ROME devoted to the study and eventually the design of appropriate network solutions. This cluster will not be open to users and will be based on FPGA technologies.Speaker: Daniele Cesini (CNAF)
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15:25
Energy vs time performances of HPC applications on Tegra K1 30mEnergy efficiency is lately becoming of paramount importance in the HPC field and high-end processors are quickly evolving towards more advanced power-saving and power-monitoring technologies. On the other hand, low-power processors, designed for the mobile market, are gaining interest in the HPC area thanks to their increasing computing capabilities, in conjunction with their competitive pricing and low power consumption. In this work we explore energy and computational performances of a Tegra K1 mobile processor, in the context of HPC, using a Lattice Boltzmann application as a benchmark. Current drawing of the board is monitored with custom hardware for different CPU, GPU and memory clocks.Speaker: Enrico Calore (FE)
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15:55
Triggering Events with GPUs at ATLAS 20mThe growing complexity of events produced in LHC collisions demands more and more computing power both for the on line selection and for the offline reconstruction of events. In recent years, the explosive performance growth of massively parallel processors like Graphical Processing Units both in computing power and in low energy consumption, make GPU extremely attractive for using them in a complex high energy experiment like ATLAS. Together with the optimization of reconstruction algorithms exploiting this new massively parallel paradigm, a small scale prototype of the full ATLAS High Level Trigger exploiting GPU has been implemented. We discuss the integration procedure of this prototype, the achieved performance and the prospects for the future.Speaker: Lorenzo Rinaldi (BO)
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16:15
Event building for the LHCb Upgrade 30mDuring the LHC Run 1 the LHCb experiment has successfully performed a large number of world-class precision measurements in heavy flavour physics by having collected over 3 fb-1 at centre-of-mass energies of 7 TeV and 8TeV. However, even after an additional expected integrated luminosity of 5-6 fb-1 in Run 2, many of the LHCb measurements will remain limited by statistics. The current 1 MHz readout system is the main bottle neck to run LHCb at higher luminosity and with higher trigger efficiencies. LHCb will therefore undergo a major upgrade in the Long Shutdown 2 of LHC (2018- 2019) aimed at collecting an order of magnitude more data by 2028. The upgrade consists of a new full readout at the LHC bunch crossing rate (40 MHz) with the ultimate flexibility of only a software trigger. In order to increase the instantaneous luminosity five times, up to 2x10^33 cm-2s-1, several sub-detector upgrades are also underway, such to cope with the expected higher occupancies and radiation dose. The talk will focus on the PCIe based readout and the Event Builder we are developing in collaboration of INFN Bologna, INFN-CNAF and the LHCb Online CERN group.Speaker: Domenico Galli (BO)
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16:45
Pausa caffè 30m
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17:15
NaNet: a Family of FPGA-based Network Interface Cards for Real-Time Trigger and Data Acquisition Systems in HEP Experiments. 30mNaNet is a modular design of a family of FPGA-based PCIe Network Interface Cards specialized for low-latency real-time operations. NaNet features a Network Interface module that implements RDMA-style communications both with the host (CPU) and the GPU accelerators memories (GPUDirect RDMA) relying on the services of a high performance PCIe Gen2/3 x8 core. NaNet I/O Interface is highly flexible and is designed for low and predictable communication latency: a dedicated stage manages the network stack protocol in the FPGA logic offloading the host operating system from this task and thus eliminating the associated process jitter effects. Between the two above mentioned modules, stand the data processing and switch modules: the first implements application-dependent processing on streams, e.g. performing compression algorithms, while the second routes data streams between the I/O channels and the Network Interface module. This general architecture has been specialized up to now into three configurations, namely NaNet-1, NaNet3and NaNet-10 in order to meet the requirements of different experimental setups. NaNet-1 features a GbE channel plus three custom 20 Gbps serial channels, NaNet3 supports four custom 2.5 Gbps deterministic latency optical channels while NaNet-10 features four 10GbE SFP+ ports.We will provide performance results for the three NaNet implementations and describe their usage in the CERN NA62 and KM3NeT-IT underwater neutrino telescope experiments, showing that the architecture is very flexible and yet capable of matching the requirements of low-latency real-time applications with intensive I/O tasks involving the CPU and/or the GPU accelerators.Speaker: Alessandro Lonardo (ROMA1)
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- 18:15
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14:45
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20:00
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23:00
Cena sociale 3h
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09:00
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13:00
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09:00
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13:00
Nuove tecnologie SoftwareConveners: Dario Livio Menasce (MIB), Dr Francesco Giacomini (CNAF), Roberto Alfieri (PR)
- 09:00
- 10:00
- 10:30
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10:50
Pausa caffè 20m
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11:10
Exascale: challenges and opportunities in a power constrained world 30mThe top500 list of last November shows for the first time a clear sign of slow down in the growing rate of supercomputers power. Not only just one new system enter in the top10 (wrt June 2014), but also the last system of the top500 display very little performance improvement. It is not a mistary that the long standing Moore's low is approaching an inevitable decline. Two factors mostly contribute to this trend: little improvement in silicon chips and power constraints. For many datacenters the capacity in term of electrical power is coming to its limit, and without a dramatic improvement in computing efficiency this limit determine the maximum size of the high-end system that can be deployed. To make Exascale a reality by the ends of the decade dramatic changes in datacenters, architectures and in particular software paradigm need to be faced. In this talk the challenges and opportunities related to these changes will be discussed and confronted with the roadmap to exascale systems.Speaker: Dr Carlo Cavazzoni (CINECA)
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11:40
Portability, Efficiency and Maintainability: the case of OpenACC 30mAn increasing number of HPC systems adopt heterogeneous node architectures, combining traditional multi-core CPUs with energy-efficient massively parallel accelerators, such as GPUs. The need to exploit the computing power of these systems, in conjunction with the lack of standardization in their hardware and/or programming frameworks, raises new issues with respect to scientific software development choices, which strongly impact software maintainability, portability and performance. Several new programming environments have been introduced recently, in order to address these issues. In particular, the OpenACC programming standard has been designed to ease the software development process for codes targeted for heterogeneous machines, helping to achieve code and performance portability. In this talk we present the OpenACC language as a tool to design, port and optimize codes intended to be portable across present and future heterogeneous HPC architectures.Speaker: Dr Enrico Calore (INFN, Sezione di Ferrara)
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- 12:40
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13:30
Presentazione SUPERMICRO: "Attuali trend nello sviluppo di tecnologie e componenti hardware a supporto delle esigenze di HPC" 30mObiettivo della presentazione è quello di fare il punto su quali tecnologie e relativi componenti hardware di recente introduzione nelle architetture dei server possono favorire e migliorare le prestazioni degli stessi per un loro migliore utilizzo in ambito HPC. In particolare si tratteranno argomenti in ambito SSD, RAM e Coprocessori. Inoltre verranno presentati le linee di sistemi Supermicro che già offrono al loro interno l’utilizzo di queste tecnologie e componenti.Speaker: Luca Arduini (SUPERMICRO)
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13:30
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14:45
Pausa pranzo 1h 15m
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14:45
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18:45
Attività dei gruppi di lavoro della CCRConveners: Luca Giovanni Carbone (MIB), Michele Michelotto (PD), Dr Paolo Lo Re (NA), Sandra Parlati (LNGS)
- 14:45
- 15:15
- 15:45
- 16:35
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16:45
Pausa caffè 30m
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17:15
!CHAOS: a Cloud of Controls 30m!CHAOS è un framework dedicato al controllo, monitoraggio, acquisizione e archiviazione dati di sensori e sottosistemi complessi. L'obiettivo di !CHAOS è di studiare e implementare un prototipo di Control as a Service. Nella presentazione verrano descritte le problematiche infrastrutturali, le soluzioni tecnologiche utilizzate per garantire la massima scalabilità in ottica di un deployment in ambiente cloud.Speakers: Michele Antonio Tota (LNF), Ramon Orrù (LNF)
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12:30
Attività dei gruppi di lavoro della CCRConveners: Luca Giovanni Carbone (MIB), Michele Michelotto (PD), Dr Paolo Lo Re (NA), Sandra Parlati (LNGS)
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09:00
CEPH come soluzione di storage consolidation 30mVerrà presentata l’attività svolta a Bari su CEPH sia come backend per i componenti dell’infrastruttura cloud sia come soluzione di storage per la farm. Verranno riportati i risultati ottenuti in termini di performance, stabilità operativa, flessibilità e semplicità di gestione. Verranno anche descritte le configurazioni adottate che permettono di implementare il tiering dello storage consentendo il caching automatico dei dati maggiormente utilizzati e il supporto QoS del Block Storage.Si descriveranno anche i metodi studiati per il deployment e la configurazione automatica di Ceph: in particolare di Puppet scelto come tool unico per gestire sia la farm sia l’infrastruttura cloud.Speaker: Marica Antonacci (BA)
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09:30
Studio di un sistema di e-voting per l'INFN 30mLa presentazione ha lo scopo di introdurre il lavoro preliminare svolto nella definizione di un sistema di e-voting per utilizzo interno da parte dell'INFN. Vengono brevemente discusse la fase di analisi dei requisiti e la valutazione delle soluzioni già esistenti che verranno utilizzate come base per l'implementazione successiva. Vengono inoltre individuate le attività di sviluppo software necessarie a garantire le caratteristiche richieste.Speaker: Ramon Orrù (LNF)
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11:30
Pausa caffè 30m
- 12:00
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09:00
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12:30
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13:00
Chiusura dei lavori 30mSpeakers: Claudio Grandi (BO), Dario Livio Menasce (MIB)
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12:30