24–30 May 2015
Europe/Rome timezone
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Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

28 May 2015, 17:42
Poster S5 - Front End, Trigger, DAQ and Data Management Front end, Trigger, DAQ and Data Management - Poster Session

Speaker

Alessandra Camplani (INFN Milano, Italy)

Description

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace expensive custom application specific integrated circuits in front end electronics in locations with moderate radiation field. The use of a FPGA in HEP experiments is only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field. In this paper, we summarize results of a two-year study of Xilinx 7-series devices on their susceptibility to a HEP experiment radiation field. Experimental results from irradiation campaigns in the USA and Europe on ionizing dose studies up to 300 krad, and single event effects measurements performed with high-energy neutrons up to 1x10exp11 n/cm2 and protons up to 1x10exp13 p/cm2, will be presented. After the proton exposure, the devices tested presented no permanent operational failure except for a 10% increase in the core-logic power consumption, well within the component specification. To mitigate single event upsets we have implemented techniques such as Triple Module Redundancy (TMR) and soft error scrubbing. The effectiveness of these implementations will be presented in detail. The paper also describes the various errors detected in the FPGA Multi Gigabit Transceivers (MGT). The estimated lane error rate suggests that the configurable logic that interfaces with the MGT is the most sensitive part of the FPGA. Proper application of mitigation methods, however, can significantly reduce this sensitivity. Future experiments are planned with improved TMR and scrubbing mitigation.

Collaboration

Alessandra Camplani, Mauro Citterio, Chiara Meroni, Istituto Nazionale di Fisica Nucleare (INFN) Milano, Via G. Celoria 16, 20133 Milano, Italy

Matthew Cannon, Michael Wirthlin, NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA

Hucheng Chen, Kai Chen, James Kierstead, Helio Takai, Physics Department, Brookhaven National Laboratory, Upton, NY 11973-5000, USA

Binwei Deng, Chonghan Liu, Tiankuan Liu, Jingbo Ye, Southern Methodist University, Dallas, TX 75275-0100, USA

Primary author

Dr Mauro Citterio (INFN Milano, Italy)

Co-authors

Alessandra Camplani (INFN Milano, Italy) Mr Binwei Deng (SMU Dallas, USA) Chiara Meroni (INFN Milano, Italy) Chonghan Liu (SMU Dallas, USA) Dr Helio Taki (Brookahaven National Laboratory) Mr Hucheng Chen (Brookhaven National Laboratory) Mr James Kierstead (Brookhaven National Laboratory) Dr Jingbo Ye (SMU Dallas, USA) Mr Kai Chen (Brookhaven National Laboratory) Mr Liu Tiankuan (SMU Dallas, USA) Mr Matthew Cannon (BYU, Provo, USA) Dr Mike Wirthlin (BYU, Provo, USA)

Presentation materials