Introduction to VHDL for FPGAs: some examples of simple logic
Slides
3
Exercise:
write code for a 16 bit register - check syntax - synthesis
write code for a MUX: from two 16 bits inputs to one 16 bit but output - check syntax - synthesis
write code for a 8 bit counter - check syntax - synthesis
write code for a comparator - check syntax - synthesis
If time in addition: write top level putting together the MUX, the regs, the comparator as shown in the figure - check syntax - synthesis
12:30
Lunch time
4
How to perform behavioural simulation
Slides
5
exercise: use of the ISE simulation
simulate and check the VHDL code written in the morning
Exercise: add the Input Fifos and the Spy buffer to the project
- generate the FIFO and RAM modules
- insert them in the top level and connect them to rest of the logic
- synthesis
- reports
- behavioral simulation
12:30
Lunch
14
Implementation
- brief description of Map, Place & root
- options
- simulation after implementation
15
brief introduction to other ISE tools - one example of design Floorplanning
- Constraint Editor
- PlanAhead - just mentioned (no time to use it) - you can exercise by yourself after 17 pm
- Timing Analyzer - just mentioned (no time to use it) - you can exercise by yourself after 17 pm
- FPGA Editor - just mentioned (no time to use it) - you can exercise by yourself after 17 pm
- XPower Analyzer - just mentioned (no time to use it) - you can exercise by yourself after 17 pm
- iMpact - will be used in the Lab session
document
Slides
16
Exercise: implementation and post-imp simulation
- implement the project with defaults
- simulation post implementation
- analysis of reports, in particular timing results
- use of the constraint editor, put the output registers in the pads
- if time is enough, look the project with PlanAhead
