Name: IAPP school: VHDL design
Start: 2013-07-01T09:00:00+02:00
End: 2013-07-04T18:00:00+02:00
Location: INFN-Pisa

IAPP school: VHDL design

from Monday, 1 July 2013 (09:00) to Thursday, 4 July 2013 (18:00)

Monday, 1 July 2013

09:00 Field Programmable Gate Arrays (FPGA)
Field Programmable Gate Arrays (FPGA)
09:00 - 09:30
Room: 250

09:30 Introduction to VHDL for FPGAs: some examples of simple logic
Introduction to VHDL for FPGAs: some examples of simple logic
09:30 - 10:30
Room: 250

10:30 Exercise:
Exercise:
10:30 - 12:30
Room: 250 write code for a 16 bit register - check syntax - synthesis write code for a MUX: from two 16 bits inputs to one 16 bit but output - check syntax - synthesis write code for a 8 bit counter - check syntax - synthesis write code for a comparator - check syntax - synthesis If time in addition: write top level putting together the MUX, the regs, the comparator as shown in the figure - check syntax - synthesis

12:30 Lunch time
Lunch time
12:30 - 14:30
Room: 250

14:30 How to perform behavioural simulation
How to perform behavioural simulation
14:30 - 15:00
Room: 250

15:00 exercise: use of the ISE simulation
exercise: use of the ISE simulation
15:00 - 17:00
Room: 250 simulate and check the VHDL code written in the morning
Tuesday, 2 July 2013

09:30 VHDL: Finite State Machines
VHDL: Finite State Machines
09:30 - 10:00
Room: 250

10:00 What does our specific FSM
What does our specific FSM
10:00 - 10:30
Room: 250

10:30 Exercise
Exercise
10:30 - 12:30
Room: 250 - write code of the FSM that can handle the flux of data of the attached figure - check syntax - synthesis

12:30 Lunch time
Lunch time
12:30 - 14:30
Room: 250

14:30 the test bench
the test bench
14:30 - 15:00
Room: 250

15:00 Exercise
Exercise
15:00 - 17:00
Room: 250 - Create a test bench for the flux of data and the FSM. - Simulate simple events flowing in the system.
Wednesday, 3 July 2013

09:30 FPGA Implementation
FPGA Implementation
09:30 - 10:00
Room: 250

10:00 FIFO and RAM from Core Generator to the VHDL code
FIFO and RAM from Core Generator to the VHDL code
10:00 - 10:30
Room: 250

10:30 Exercise: add the Input Fifos and the Spy buffer to the project
Exercise: add the Input Fifos and the Spy buffer to the project
10:30 - 12:30
Room: 250 - generate the FIFO and RAM modules - insert them in the top level and connect them to rest of the logic - synthesis - reports - behavioral simulation

12:30 Lunch
Lunch
12:30 - 14:30
Room: 250

14:30 Implementation
Implementation
14:30 - 14:50
Room: 250 - brief description of Map, Place & root - options - simulation after implementation

14:50 brief introduction to other ISE tools - one example of design Floorplanning
brief introduction to other ISE tools - one example of design Floorplanning
14:50 - 15:05
Room: 250 - Constraint Editor - PlanAhead - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - Timing Analyzer - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - FPGA Editor - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - XPower Analyzer - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - iMpact - will be used in the Lab session

15:05 Exercise: implementation and post-imp simulation
Exercise: implementation and post-imp simulation
15:05 - 17:05
Room: 250 - implement the project with defaults - simulation post implementation - analysis of reports, in particular timing results - use of the constraint editor, put the output registers in the pads - if time is enough, look the project with PlanAhead
Thursday, 4 July 2013

09:30 Chipscope and debugging
Chipscope and debugging
09:30 - 10:00
Room: 250

10:00 Isertion of chipscope in the project -
Isertion of chipscope in the project -
10:00 - 10:30
Room: 250

10:30 CAEN demonstration: introduction about the boards
CAEN demonstration: introduction about the boards
10:30 - 11:00
Room: 250

11:00 Hands on in the LAB
Hands on in the LAB
11:00 - 12:30
Room: 250

12:30 Lunch
Lunch
12:30 - 14:30
Room: 250

14:30 Lab Session
Lab Session
14:30 - 16:30
Room: 250 - simple CAEN demonstration - programming chips in the FTK crate - Logic running in the FTK crate - chipscope use -oscilloscope use