24–30 May 2015
Europe/Rome timezone
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The WaveCatcher Waveform Digitizers: high-end instrumentation for characterization of advanced fast detectors

28 May 2015, 17:28
Poster S5 - Front End, Trigger, DAQ and Data Management Front end, Trigger, DAQ and Data Management - Poster Session

Speaker

Mr Dominique Breton (CNRS / IN2P3 / LAL Orsay)

Description

TThe WaveCatcher digitizers are proposing an alternative to oscilloscopes or ADC-based digitizers. They are based on the SAMLONG Switched Capacitor Array (AMS CMOS 0.35-µm). This circuit permits sampling high speed signals like very short pulses (range of 2.5 V, 12 bits coding, 500 MHz bandwidth, sampling rate between 0.4 and 3.2 GS/s). The sampling depth is of 1024 samples, which fits with most applications where readout dead-time is not critical. The number of channels of the WaveCatcher digitizers ranges from 2 for the USB-powered version to 64 (optionally 72). Sampling time precision is better than 5 ps rms, which permits using the system as a high-resolution TDC between any set of channels, the time precision remaining constant between chips and boards. Moreover, the boards and systems offer a lot of functionalities, like threshold-triggering on any channel and numerous trigger modes including smart coincidences. A firmware block located in each channel permits performing on-board real-time extraction of the main signal characteristics (amplitude, charge, time, …) , and individual rate counters are also implemented. In parallel to hardware and firmware, we developed a powerful and user friendly acquisition software running on PC and transforming the latter into a 2 to 64-channel oscilloscope. It permits saving data files directly on disk, and is currently used in most WaveCatcher system applications. A C-library is also available for Windows or Linux code development.

Summary

Fast particle detectors are implied in all kinds of applications. Fast signals can also be produced by captors mounted on particle accelerators. Associated electronics can be used either for their characterization (test benches) or for their readout (physics experiments or medical apparatus).
In the case of test benches, ultimate performance of the electronics over a limited number of channels is required whereas in the case of physics experiments, the target is the best compromise between small cost per channel and power consumption, and a high level of performance.
As it will be shown here, waveform digitizing with analog memories permits reaching all these goals. Indeed, this solution offers a very high precision both for amplitude (12-bit resolution) and time measurement (picosecond level) but also the possibility of a high level of integration. It can thus be used in almost all cases where SCA readout dead-time is not critical (between 12 and 125 µs depending on the readout conditions).
The recent progresses in the field of particle-detection have pushed the performances of the detectors toward very fast signals and time measurement at the picosecond scale. This is especially true for MCP-PMTs (Micro-Channel Plate PMTs), and tends to be the case for the upcoming generations of diamonds, fast silicon sensors and SiPMs. The usual solution dedicated to precise charge and time measurements for test or characterization benches is mainly based on the use of high-end oscilloscopes. But their cost per channel is high and their number of channels very limited. Numerous test benches were also based on commercial modules, both Charge-to-Amplitude Converters and Constant Fraction Discriminators (CFD) associated with Time to Digital Converters (TDC). The time resolution obtained with some of these modules, like the ORTEC 9327CFD, TAC588, and 14bit ADC114 electronics, is very good (~ 5 ps rms after time-walk correction), but they are expensive and house very few channels. Some TDC boards offer a higher number of channels, using multi-channel TDC ASICs based on a coarse measurement performed by a digital counter associated with a fine measurement (interpolation) using Delay Line Loops, but their overall resolution is today limited to ~ 25 ps rms. One of the reasons is the need for a discriminator to transform the incoming analog signal into digital in front of the TDC, which is a source of extra jitter. Recent works are reporting the integration of high-precision TDCs inside high-end FPGA with an impressive level of performance. New generation DLL-based TDCs are also under study. But these solutions suffer from the need of a discriminator the same way as the current TDC ASICs.
Recently, the progress in the field of waveform digitizers permitted the development of alternative methods for amplitude, charge and time measurements. They are based on digital treatment of the analog sampled then digitized detector signal. Such methods permit a straightforward calculation of the charge and amplitude, and achieve a timing resolution far better than the sampling frequency thanks to signal interpolation. Digitization systems have actually followed the progress of commercial ADCs, but the latter exhibit large drawbacks like their huge output data rate and power consumption. They thus require the use of very high-end FPGAs to treat the data flux, thus introducing extra cost and complexity. Conversely, high speed analog memories now offer sampling rates far above 1 GS/s over 12 bits at low cost and with low power consumption. Moreover, their companion FPGA can be low-end, thus also low-power and low-cost
The WaveCatcher boards and systems have thus been developed for proposing an alternative to oscilloscopes and ADC-based digitizers. They are based on the SAMLONG SCAs developed since 2010 with the AMS CMOS 0.35-µm technology. All boards offer a wide DC-coupled dynamic range of 2.5 V (with adjustable offset) coded over 12 bits, a bandwidth of 500 MHz and a sampling rate ranging between 3.2 and 0.4 GS/s, which allows them to finely sample high speed signals like very short pulses. The sampling depth is of 1024 samples, which is adequate for most applications. The number of channels goes from 2 for the USB-powered version packaged in a friendly plastic box, to 64 (optionally 72) for the version housed in an autonomous mini-crate (available versions house 2, 8, 16, 32, 48 and 64 channels). Thanks to the servo-controlled matrix structure of SAMLONG and the care taken in the board design, the sampling time precision is better than 5 ps rms. This permits using the system as an absolute time stamper, or as a high-resolution TDC between any set of channels, the time precision remaining constant between chips and boards. The boards offer a lot of functionalities, like threshold-triggering on any channel and numerous smart trigger modes including coincidence. A firmware block located in each channel permits performing on-board real-time extraction of the signal characteristics (baseline, amplitude, charge, rising & falling edges (via fixed threshold crossing or constant fraction discrimination)). Individual rate counters are implemented in each channel. All system versions house a 480-Mbits/s USB interface permitting an easy connection to PC and a good readout speed, and most of them also offer a 1 Gbit/s UDP interface.
In parallel to hardware and firmware developments, we developed a powerful and user-friendly acquisition software running on PC and transforming the latter into a 2 to 64-channel oscilloscope. It is currently ran by most board users. It permits performing many types of measurements and their real-time histogramming, and saving data to files in ASCII or binary format. C-libraries have also been written, permitting easy code development under Windows or Linux. All these tools permit an almost immediate use of the boards and modules.
An increasing number of labs or companies are now using the WaveCatcher boards worldwide on their test benches or physics experiments. For instance, it permits fully characterizing with a very high precision a 64-channel detector in one single run. It also permits measuring the noise rate of multiple SiPMs in parallel with respect to their whole signal amplitude range within a few tens of seconds. In the frame or astroparticle physics, 320-channel 6U crates have been developed for the SuperNemo neutrino experiment, and they will be deployed in the Modane underground laboratory in 2015.

Primary authors

Mr Dominique Breton (CNRS / IN2P3 / LAL Orsay) Mr Eric Delagnes (CEA / DSM / Irfu) Mrs Jihane Maalmi (CNRS / IN2P3 / LAL Orsay)

Co-author

Mr Pascal Rusquart (CNRS / IN2P3 / LAL Orsay)

Presentation materials