INFN Mezzanine

22 Sept 2015, 14:00 → 24 Sept 2015, 15:00 Europe/Rome

250

Review the status of the FW, the experience gained on AM05 mezzanine and discuss the next mezzanine AM06

Tuesday, 22 September

15:30 → 16:00 Goal of the meeting, the next months

Speaker: Fabrizio Palla (PI)

Slides LyonKITPisa.ppt

16:00 → 16:45 Geometry, pattern banks and data formats

Speaker: Dr Sebastien Viret (CNRS/IN2P3)

Slides L1AM_220915.pdf

16:45 → 17:15 Status of the PCA (in C++) and its floating point implementation

Speaker: Loriano Storchi (P)

Slides results_PCA.pdf

17:15 → 17:45 Thermal analysis of the mezzanine

Slides AM0X_Thermal_Simulation.ppt

Wednesday, 23 September

09:00 → 09:30 Lookup table and constants

Slides lookupTable_INFN.pdf

09:30 → 10:00 Filtering/reducing combinations FW

Slides Pres_Geoffrey_23_09_15.pdf

10:00 → 10:20 Filtering/reducing combinations 2

Speaker: Massimo Casarsa (TS)

Slides retina-1.pdf

10:20 → 10:50 Pausa caffe'

10:50 → 11:20 Status of DO and TF firmware

Speaker: Christos Gentsos (Auth)

Slides INFN_mezzanine_meeting_23-9.pdf

11:20 → 11:50 Status of AM06 chip and changes wrt AM05

Speaker: Alberto Annovi (PI)

Slides CMSmeeting_aPisa_20150922.pdf

11:50 → 12:20 Aurora link firmware status

Speaker: Guido Magazzu' (PI)

Slides Pisa_Sep23.pdf

12:30 → 14:00 Pausa pranzo

14:00 → 15:00 Status of the AM05 mezzanine tests - what have we learned?

Speakers: DANIEL MAGALOTTI (PG), Giacomo Fedi (PI), Guido Magazzu' (PI)

Slides AMFPGA16Sep22.pdf

15:00 → 16:00 Proposed changes for the AM06 mezzanine

Slides bruno_NEW_PRM.pdf Per_la_prossima_with_Perugia_comments_(1).doc

16:00 → 16:30 Pausa caffe'

16:30 → 17:30 Attendance of the General CMS L1 track trigger meeting

Thursday, 24 September

09:00 → 10:00 Discussion on mezzanine qualification procedures

Speaker: Bruno Checcucci (PG)

10:00 → 10:30 Discussion on firmware integration policy

Slides PRM_fw_modified_Fabrizio.pptx

10:30 → 11:00 Pausa caffe'

11:00 → 12:00 Signup for the AM06 mezzanine work and item distribution

Test 4 AM blocks cross talk and operations with 4 AM blocks (including sync) Check the power budget of the mezzanine (measurements and availability from the Pulsar 2b, including external power) Check the clock jitter. Clock should be changed anyway to match Xilinx specs. Check external memory needs. Measure the time of access. Decide which type. Evaluate resources needs for the FPGA including all FW. Evaluate the time to modify the PCB for 8 AM chips Evaluate the time to modify the PCB to accommodate the needed changes NB: the last 2 items depend on how many engineers will be working. So Time and FTE estimates.

12:00 → 12:30 Plan for the next months