Introductory course to VHDL and HLS FPGA programming

23 Jun 2025, 09:30 → 27 Jun 2025, 18:00 Europe/Rome

Università degli Studi Milano Bicocca

Introduction to FPGA programming

Image taken from: https://https://digilent.com

The course is mainly thought for the new personnel hired by means of the ICSC project to work on projects and research activities in the framework of Spoke 2 ("Fundamental Research And Space Economy") and Spoke3 (Astrophysics & Cosmos Observations), but open to anyone interested within the fundamental physics community.

Lecturers: 

• Andrea Triossi (University of Padova) 
• Mirko Mariotti (University and INFN of Perugia)
• Sioni Summers (CERN)

 

Facilitators for the hands-on sessions: 

• Giulio Bianchini (INFN of Perugia)
• Francesco Brivio (INFN Milano Bicocca)

 

Prerequisites: 

• Basic notion of digital electronics (combinatorial and sequential circuits)
• basic C++ programming with usage of  templates
• basic python programming
• entry level knowledge of machine learning (not really needed, but it may help for the last part of the course)

 

Target skills and knowledge: The aim of the course is to provide a hands-on programming laboratory of Field-Programmable Gate Arrays (FPGA) through the VHDL hardware description language 

Course unit contents:

• Introduction to FPGAs
• FPGA Architecture
• FPGA programming flow
• VHDL language by examples
  • Introduction to the Vivado programming framework and the Arty A7 board
  • Combinational circuits on FPGA
  • Sequential circuits on FPGA
  • Arithmetic operations on FPGA
• Case study: UART interface
• High Level Synthesis (HLS)
  • Programming flow
  • Number representations and arithmetic
  • Loops: understanding and optimizing
• HLS case study: Missing transverse energy calculation

 

Suggested readings:

• Manual for syntax
  • The VHDL Golden Reference Guide (DOULOS)
  • VHDL handbook (HARDI)
• Books
  • Zwolinski,M., Digital System Design with VHDL. Harlow: PRentice Hall Pearson Education
  • Tappero F., Mealy B., Free Range VHDL
  • Kastner R., Matai J., Neuendorffer S., Parallel Programming for FPGAs

 

All the participants are requested to have a copy of Vivado installed on a local machine

The Course will be held at  Università degli Studi di Milano Bicocca

GitHub pages:

• Day 1: https://github.com/FPGA-course-2025/day1
• Day 2: https://github.com/FPGA-course-2025/day2
• Day 3: https://github.com/FPGA-course-2025/day3
• Day 4: https://github.com/FPGA-course-2025/day4
• Day 5: https://github.com/FPGA-course-2025/day5

 

Monday, 23 June

09:30 → 12:45 Introduction to VHDL

09:30 Introduction to FPGAs

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

Intro.pdf

10:00 FPGA design flow

Source files, Intellectual Property files, constraints files, Simulation, Synthesis, Implementation, Debugging

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

Design_flow.pdf

11:00 Coffe break

11:30 FPGA architecture

Overview of all the elements of an FPGA. Configurable logic blocks, Switch Matrix, I/O blocks, Look Up Tables, Storage elements, Memories, Shift registers, Multiplexers, Carry logic, Clock distribution, Clock buffers, Clock Management tile, FIFOs, Digital Signal Processors

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

FPGA_architecture.pdf

12:30 → 13:30 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

12:30 Vivado environmet

https://github.com/FPGA-course-2025/day1

Speaker: Mirko Mariotti (Istituto Nazionale di Fisica Nucleare)

14:30 → 19:00 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

14:30 Vivado environment

Speaker: Mirko Mariotti (Istituto Nazionale di Fisica Nucleare)

15:30 Combinatorial functions in VHDL

Basic examples of combinatorial functions in VHDL. VHDL types and type conversions

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

VHDL_by_ex_2.pdf

16:30 Coffee break

17:00 Combinatorial functions in VHDL

Basic examples of combinatorial functions in VHDL. VHDL types and type conversions

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

Tuesday, 24 June

09:30 → 14:00 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

09:30 Arithmetic operation in VHDL

Case study: the adder. Simulation of VHDL code through test bench

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

11:00 Coffee break

11:30 Sequential circuits in VHDL

Sequential circuits in VHDL Example of sequential circuits: flip-flop, latch, shift register, counter. Reset circuit strategies. Flash Programming

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

14:30 → 19:00 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

14:30 Sequential circuits in VHDL

Synchronous logic design. Inference in VHDL. State machines

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

16:30 Coffee break

17:00 Debugger

How to place a debugger on the design: pre and post synthesis

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

Wednesday, 25 June

09:30 → 14:00 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

09:30 UART transmitter unit

Interface of the Arty A7 board. Introduction of the RS232 standard.

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

UART.pdf

11:00 Coffee break

11:30 UART receiver unit

Implementation and simulation in VHDL of a UART receiver unit

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

14:30 → 18:30 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

14:30 Verilog

Speaker: Mirko Mariotti (Istituto Nazionale di Fisica Nucleare)

course.pdf

15:30 Open source FPGA tools

Speaker: Mirko Mariotti (Istituto Nazionale di Fisica Nucleare)

16:30 Coffee break

17:00 Zynq, Alveo and Pynq introduction

Speaker: Mirko Mariotti (Istituto Nazionale di Fisica Nucleare)

Thursday, 26 June

09:30 → 13:00 Introduction to HLS

09:30 HLS - Introduction and Numerics

• Number representations
• Fixed point arithmetic
• Getting started with HLS code & tools

Speaker: Sioni Summers

Day 4

icsc_hls_2025_sps.pdf

icsc_hls_2025_sps_p1_w_solutions.pdf

Vitis_HLS_On_Cloud.pdf

11:00 Coffee break

11:30 HLS - Introduction and numerics

• Number representations
• Fixed point arithmetic
• Getting started with HLS code & tools

Speaker: Sioni Summers

arithmetic.ipynb

14:30 → 18:00 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

14:30 HLS - Introduction and Numerics

• Extended HLS exercise

Speaker: Sioni Summers

16:30 Coffee break

17:00 HLS - Interfaces

• communicating with HLS modules

Speaker: Sioni Summers

Friday, 27 June

09:30 → 13:30 Introduction to HLS

09:30 HLS - Loops

• Understanding loops
• Understanding memory
• Optimizing loops

Speaker: Sioni Summers

11:00 Coffee break

11:30 HLS - Loops

• Understanding loops
• Understanding memory
• Optimizing loops

Speaker: Sioni Summers

icsc_hls_2025_sps_p2_w_solutions.pdf

MET solution

$ git pull origin solutions
From https://github.com/FPGA-course-2025/day4
 * branch            solutions  -> FETCH_HEAD
Updating 62ddc13..9be648a
Fast-forward
 MET/cosim.tcl           |    2 +-
 MET/csim.tcl            |    4 +-
 MET/csynth.tcl          |    4 +-
 MET/example_met.cpp     |   15 +
 MET/example_met.h       |   18 +
 MET/met_hls.csv         | 2000 +++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------
 MET/met_hls_float.csv   | 1000 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 MET/met_reference.ipynb |  198 +++++++++--
 MET/testbench.cpp       |    2 +-
 uart/VHDL/top.vhd       |   18 +-

 

14:30 → 18:00 Hands on

Day 1

Day 2

Day 3

Day 4

Day 5

FPGAs_list.pdf

On Linux:

picocom -b 115200 -r -l /dev/ttyUSB0

 

On Mac:

screen /dev/[port name] [baud rate]

for example:

screen /dev/ttyUSB0 115200

 

---

vitis_hls 

If you use Vitis_HLS in the  cloud environment you have to change one command in the .tcl file.

Change from

csim_design

to 

csim_design -ldflags "-fuse-ld=gold"

14:30 The BondMachine Project

Speaker: Mirko Mariotti (Istituto Nazionale di Fisica Nucleare)

FPGA_Course_2025.pdf