Test 4 AM blocks cross talk and operations with 4 AM blocks (including sync)
Check the power budget of the mezzanine (measurements and availability from the Pulsar 2b, including external power)
Check the clock jitter. Clock should be changed anyway to match Xilinx specs.
Check external memory needs. Measure the time of access. Decide which type.
Evaluate resources needs for the FPGA including all FW.
Evaluate the time to modify the PCB for 8 AM chips
Evaluate the time to modify the PCB to accommodate the needed changes
NB: the last 2 items depend on how many engineers will be working. So Time and FTE estimates.