Energy consumption, conversion, and transfer in nanometric Field-Effect-Transistors (FET) used in readout electronics at cryogenic temperatures

25 Jul 2019, 17:45
1h 15m
Piazza Città di Lombardia (Milano)

Piazza Città di Lombardia

Milano

Piazza Città di Lombardia, 1, 20124 Milano MI
Poster Detector readout, signal processing, and related technologies Poster session

Speaker

Mr Alfonso Cabrera (National Institute of Astrophysics, Optics, and Electronics (INAOE) )

Description

For integrated FET based circuitry in close proximity to the front-end detectors or semiconductor or superconducting qubit generating hardware held at cryogenic temperatures, any transfer of heat produced in the FET circuitry alters the performance conditions of the system and results in noise and spurious signals. Therefore, it is of great interest to analyze and experimentally characterize the processes of heat generation at the transistor level, the heat transport mechanisms from the intrinsic active region of the transistor to the interconnection metal lines, the substrate, and finally the entire circuit itself.
We introduce the analysis and experimental results of the energy consumption, the energy transfer mechanisms, and the process of conversion of electrical energy into heat. The different heat transfer mechanisms that consider the contributions of phonons and electrons, respectively, are modeled as a function of the FET technology parameters including gate oxide thickness, bulk and source/drain doping, and the device geometry and structure. This model serves the purpose of calculating the intrinsic device temperature, the amount of self-heating, and the coupled electro-thermal transport effects at sub-Kelvin temperatures.
We prove that as the temperature is reduced down to the sub-Kelvin regime, more than 70% of the heat in the transistor is transferred by electrons rather than phonons, and that such a heat transfer is a function of the gate oxide thickness, as well as the bulk and source/drain doping levels. The characterization and modeling of the thermal behavior and its coupling to the electrical performance is crucial in determining the electrical-thermal cross coupling. FETs fabricated in 65nm and 14nm CMOS technologies are characterized from room temperature down to 250 mK.

Student (Ph.D., M.Sc. or B.Sc.) Y
Less than 5 years of experience since completion of Ph.D Y

Primary authors

Mr Omar López-López (National Institute of Astrophysics, Optics, and Electronics (INAOE)) Mr Ismael Martínez (1National Institute of Astrophysics, Optics, and Electronics (INAOE)) Mr Alfonso Cabrera (National Institute of Astrophysics, Optics, and Electronics (INAOE) ) Dr Edmundo A. Gutiérrez-D. (1National Institute of Astrophysics, Optics, and Electronics (INAOE)) Dr Daniel Ferrusca (National Institute of Astrophysics, Optics, and Electronics (INAOE)) Dr Daniel Durini (National Institute of Astrophysics, Optics, and Electronics (INAOE)) Dr Javier De la Hidalga-Wade (National Institute of Astrophysics, Optics, and Electronics (INAOE)) Dr Miguel Velazquez (National Institute of Astrophysics, Optics, and Electronics (INAOE)) Dr Ivan Quiroga (National Institute of Astrophysics, Optics, and Electronics (INAOE)) Dr Andre Kruth (Central Institute of Engineering, Electronics and Analytics ZEA-2 – Electronic Systems, Forschungszentrum Jülich GmbH) Dr Carsten Degenhardt (Central Institute of Engineering, Electronics and Analytics ZEA-2 – Electronic Systems, Forschungszentrum Jülich GmbH) Mr Anton Artanov (Central Institute of Engineering, Electronics and Analytics ZEA-2 – Electronic Systems, Forschungszentrum Jülich GmbH) Dr Stefan van Waasen (Central Institute of Engineering, Electronics and Analytics ZEA-2 – Electronic Systems, Forschungszentrum Jülich GmbH)

Presentation Materials