Speaker
Mr
Daniel Hugo Campora Perez
(CERN)
Description
The LHCb trigger is a real time system with high computation requirements, where incoming data from the LHCb detector is analyzed and selected by applying a chain of algorithms. The infrastructure that sustains the current trigger consists of Intel Xeon based servers, and is designed for sequential execution. We have extended the current software infrastructure to include support for offloaded execution on manycore platforms like graphics cards or the Intel Xeon/Phi. In this paper, we present the latest developments of our offloading mechanism, and we also show feasability studies over subdetector specific problems which may benefit from a manycore approach.
Primary authors
Mr
Alexey Badalov
(La Salle - Ramon Llull University)
Mr
Daniel Hugo Campora Perez
(CERN)
Co-authors
Dr
Niko Neufeld
(CERN)
Dr
Xavier Vilasis Cardona
(La Salle - Ramón Llull)
