10–12 Sept 2014
University of Pisa
Europe/Rome timezone

INTEL HPC portfolio

12 Sept 2014, 11:30
45m
University of Pisa

University of Pisa

<a target="_blank" href=https://www.google.com/maps/place/Dipartimento+di+Fisica/@43.720239,10.407985,17z/data=!3m1!4b1!4m2!3m1!1s0x12d591bb7d8c8ec9:0xbf91ddd442e32978>Polo Fibonacci</a> Largo Bruno Pontecorvo, 3 I-56127 Pisa <em>phone +39 050 2214 327</em>

Speaker

Emiliano Politano

Description

The use of heterogeneous architectures in HPC at the large scale has become increasingly common over the past few years. One new technology for HPC is the Intel Xeon Phi co-processor that is x86 based, hosts its own Linux OS, and is capable of running most codes with little porting effort. However, the Xeon Phi architecture has significant features that are different from that of Xeon CPUs. Attaining optimal performance requires an understanding of possible execution models and the architecture. This talk highlights various options in Intel HPC portfolio.

Primary author

tbc

Presentation materials