8th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging.

The prototype of 6-bit SAR ADC for SOI pixel detector readout

Not scheduled

Sestri Levante

poster

Speaker

Ms Roma Dasgupta (University of Science and Technology AGH)

Description

Silicon-On-Insulator (SOI) technology uses an insulator layer in a standard silicon substrate CMOS structure. The reduction of parasitic capacitances to substrate increases the speed of a circuits and decreases theirs power consumption. Moreover, there is a possibility to design monolithic detectors with sensor matrix and electronic integrated on a single wafer. These features make the SOI technology a good candidate for particles detector readout systems. In this work the design and preliminary measurements of 6- bit SAR ADC is presented. The ADC was designed in 200 nm Lapis SOI and is dedicated for column readout of SOI pixel detectors developed in this technology. The first measurements show that correct operation and the ADC achieves ENOB of about 5 bits at 7~MHz of sampling frequency. The measured power consumption is about 300$\mu W$.

Summary

The SOI technology is a promising candidate for future high energy physic detector systems because of the possibility for monolithic pixel detector design. Moreover, the Burried-Oxide (BOX) layer in the SOI structure helps to reduce the power consumption of the electronic circuits and increase their speed. The additional advantages is latch-up effects elimination and significant reduction of Single Event Upsets (SEU). The proposed Analog-to-Digital Converter (ADC) is a sub-part of a complex pixel detector matrix with dedicated readout electronics, being developed by the authors of this work in 200nm Lapis Fully-Depleted, Low-Leakage SOI technology.

The Successive Approximation Register (SAR) architecture provides a good conversion speed in relation to circuit power consumption. The presented 6-bit SAR ADC uses fully differential architecture. It consists of bootstrapped switches for sampling the input signal, 2-stage dynamic comparator and a pair of capacitive DACs. The whole system is controlled by fully asynchronous static logic. Splitting the DACs matrixes and using the Merge Capacitor Switching technique allows to significantly decrease the power consumption of the ADC. Moreover, due to asynchronous operation of the logic there is no need to generate and distribute a clock tree. Since the ADC does not consume static power and uses asynchronous logic it is ready for power pulsing, as needed by readout systems of future linear colliders.

In order to test the behavior of different transistors available in 200nm Lapis SOI, three different variations of the proposed ADCs were designed. The main interest was given to the performance dependence on transistor type in the analog ADC part (bootstrap, comparator). For this blocks various configurations of source-tied, body-floating and body-tied transistor were used. The layout area of the presented 6-bit ADC is 50 $\mu m$ $\times$ 300 $\mu m$.

First measurements show that all prototypes are fully functional and there is no meaningful difference in performance for different transistor versions of ADCs, although precise measurements are still needed. The measured power consumption at 7~MS/s rate is around 300$\mu W$. The preliminary measurements show that the ENOB is about 5 bits and is similar for all ADC prototypes.  The detailed studies of ADC performance are ongoing and their results will be presented. 
The presented ADC has been implemented as column ADC and fabricated in a prototype monolithic pixel detector. The measurements of prototype pixel detector are just starting, and will be presented too.