Speaker
Description
Summary
State of the art tracking pixel detectors with precise time-tagging show a time resolution of about 200 ps [1], and we aim to reduce this by one order of magnitude. Crucial aspects to achieve this ultimate time resolution are the optimization of pixel sensor geometries (in both 3D and planar technologies) to achieve the most uniform electric field, and the design of fast and low noise dedicated front-end ASIC. This front-end will incorporate a fast current amplifier followed by a discriminator and a time-to-digital converter, and will be developed in 65 nm CMOS technology with fault tolerant architecture which matches the radiation hardness requirements.
Feasibility studies of a 4D fast track finding system, using hits’ space and time information, has been recently presented [2] as a possible solution for the low level track trigger of the HL-LHC experiments. The system is based on a massively parallel algorithm implemented in commercial FPGAs using a pipelined architecture and allows a precise real-time determination of the track parameters (including time) while maintaining a low fraction of reconstructed fake tracks.
The proposed detector will allow to perform flavour physics at LHC while operating at instantaneous luminosities more than one order of magnitude larger than the current ones, while guaranteeing large tracking efficiencies and a negligible ghost tracks rate.