Workshop della Commissione Calcolo e Reti dell'INFN - 2015 (LNF)

Session

Nuove tecnologie hardware

27 May 2015, 14:45

Aula Touschek (Laboratori Nazionali di Frascati dell'INFN)

Conveners

Nuove tecnologie hardware

• Piero Vicini (ROMA1)
• Michele Michelotto (PD)
• Daniele Cesini (CNAF)

25. Introduction

Michele Michelotto (PD), Piero Vicini (ROMA1)

27/05/2015, 14:45

26. The INFN COSA project

Daniele Cesini (CNAF)

27/05/2015, 14:55

COSA (COmputing on SoC Architectures) is an CSN5 2 years (2015-2016) project aimed at evaluating the potential, the performances and the running costs of computing systems based on low power System-on-Chip (SoC). A cluster of development boards based on SoCs will be installed and configured. It will dimensioned to run in a realistic way (i.e. for real life use cases) scientific applications...

27. Energy vs time performances of HPC applications on Tegra K1

Enrico Calore (FE)

27/05/2015, 15:25

Energy efficiency is lately becoming of paramount importance in the HPC field and high-end processors are quickly evolving towards more advanced power-saving and power-monitoring technologies. On the other hand, low-power processors, designed for the mobile market, are gaining interest in the HPC area thanks to their increasing computing capabilities, in conjunction with their competitive...

28. Triggering Events with GPUs at ATLAS

Lorenzo Rinaldi (BO)

27/05/2015, 15:55

The growing complexity of events produced in LHC collisions demands more and more computing power both for the on line selection and for the offline reconstruction of events. In recent years, the explosive performance growth of massively parallel processors like Graphical Processing Units both in computing power and in low energy consumption, make GPU extremely attractive for using them in a...

32. Event building for the LHCb Upgrade

Domenico Galli (BO)

27/05/2015, 16:15

During the LHC Run 1 the LHCb experiment has successfully performed a large number of world-class precision measurements in heavy flavour physics by having collected over 3 fb-1 at centre-of-mass energies of 7 TeV and 8TeV. However, even after an additional expected integrated luminosity of 5-6 fb-1 in Run 2, many of the LHCb measurements will remain limited by statistics. The current 1 MHz...

29. NaNet: a Family of FPGA-based Network Interface Cards for Real-Time Trigger and Data Acquisition Systems in HEP Experiments.

Alessandro Lonardo (ROMA1)

27/05/2015, 17:15

NaNet is a modular design of a family of FPGA-based PCIe Network Interface Cards specialized for low-latency real-time operations. NaNet features a Network Interface module that implements RDMA-style communications both with the host (CPU) and the GPU accelerators memories (GPUDirect RDMA) relying on the services of a high performance PCIe Gen2/3 x8 core. NaNet I/O Interface is highly flexible...

30. INFN H2020 projects for new hardware technologies

Piero Vicini (ROMA1)

27/05/2015, 17:45

31. Some experiences with Power Efficient Architectures in HEP

Mr Felice Pantaleo (CERN)

27/05/2015, 18:15