Introductory course to VHDL and HLS FPGA programming

FPGA design flow

23 Jun 2025, 10:00

1h

U6-01f (Università degli studi Milano Bicocca)

Introduction to VHDL

Speaker

Andrea Triossi (Universita` degli Studi di Padova)

Description

Source files, Intellectual Property files, constraints files, Simulation, Synthesis, Implementation, Debugging

Presentation materials

Design_flow.pdf