Speaker
Description
TThe development of large-area MCP-based particle detectors with time resolutions
of ≤5 ps [1] would allow substantive advances in particle identification at particle colliders.
We describe a preliminary design for a 7+1-channel 40 GS/sec waveform sampling ASIC in
the TSMC 65 nm process with the goal of achieving 1 ps resolution at 20 mW power per
channel. Each channel consists of four fast buffers and a slow buffer. The fast buffer is 1.6
ns long and has a nominal sampling rate of 40 GSa/second. The slow buffer is 204.8 ns long
and samples at 5 GSa/second, useful at identifying pile-up and the temporal context for
unusual signals. Recording of the data for each channel is triggered by a fast discriminator
capable of multiple triggering during the window of the slow buffer.
The sampling switches are implemented as 2.5V nMOSFETs controlled by 1.2V shift
registers in order to achieve a large dynamic range, low leakage, and high bandwidth. Stored
data are exported to be digitized by an external ADC at 10 bits or better.
Specifications on operational parameters include a 4 GHz analog bandwidth and a
deadtime of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the
choice of the external ADC.
I will present the current status.
| Role of Submitter | I am the presenter |
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