Speaker
Description
Research and development on 3D integrated digital silicon photo-multipliers is motivated by the growing interest in high-energy physics, medical and telecommunication communities. The race in particle accelerators and noble liquid experiments to enable more precise vertex reconstruction implies the need to reduce the timing jitter of the whole electronic chain while increasing the detecting area. The finer timing resolution will also enable great advances in medical imaging from time-of-flight (ToF) positron emission tomography to ToF computed tomography. To achieve the finest spacial resolutions physically possible, the whole detector chain must achieve a timing resolution below 10 ps. This timing precision also enables the adoption of the device in the telecommunication field where quantum key distribution devices benefit by of reducing the physical size of the systems and increasing the data throughput.
In this context, our group is developing a Photon-to-Digital Converter (PDC) aiming at such a timing resolution for the whole detector chain.
To achieve this, a cathode connected quenching circuit (QC) has been designed capable of actively recharging a single photon avalanche diode (SPAD) connected to its input. The prototype, designed in TSMC 65 nm LP technology, includes the full front-end chain required to detect and timestamp photons with an LSB below 10 ps. Furthermore, the prototype includes 2 arrays of 4$\times$4 quenching circuits connected to a 65 nm SPAD array as the input and to time-to-digital converters (TDC) at the output. The QC adopts an inverter chain capable of configuring its switching voltage to optimize the front-end's timing jitter and reduce spurious counts due to the input noise. To improve the production yield, the QC follows all design for manufacturing rules.
The proposed presentation follows the design process and shows updates on PDC fabrication and preliminary results on the newly developed QC prototype.
| Role of Submitter | I am the presenter |
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