Speaker
Description
The CMS ECAL barrel is set to undergo a substantial upgrade to meet the new and more challenging requirements of the High-Luminosity LHC (HL-LHC) accelerator. This upgrade involves a comprehensive redesign of the on-detector readout electronics, introducing new faster ASICs.
The upgraded readout architecture will consist of a fast trans-impedance amplifier, called CATIA, and a two-channels 12-bit 160 MS/s ADC and a data selection and compression ASIC, called LiTE-DTU. The output of each readout channel is a single 1.28 Gbps serial line, which is connected to an e-link of the lpGBT radiation tolerant transceiver. The data from all readout channels will be sent to an FPGA based data processor located outside the LHC cavern.
The CATIA serves as a trans-impedance amplifier to read signals from the APD sensors connected to the ECAL crystals. It provides two differential outputs with two different gains, x10 and x1, to optimise the resolution for signals up to 2 TeV. The LiTE-DTU ASIC integrates two 12-bit 160 MS/s successive approximation register ADCs to sample CATIA outputs. It also incorporates a gain selection mechanism and a lossless data compression algorithm, enabling efficient data transmission. The resulting data from all readout channels is transmitted to an off-detector FPGA-based data processor.
This upgrade aims to deliver high-precision energy measurements, with a significantly improved time resolution (approximately 30 ps) for photons and electrons above 50 GeV. This enhancement addresses HL-LHC challenges such as increased event pileup and improves the rejection of spike signals resulting from direct APD interactions.
Extensive testing has been carried out at both ASIC and system levels, demonstrating the readiness of all the prototypes and the system's ability to meet the time and energy resolution requirements, also in beam test settings. The highlights of these tests will be presented.
| Collaboration | CMS Collaboration |
|---|---|
| Role of Submitter | I am the presenter |
