Relatore
Descrizione
In this contribution are presented the results on the test activity on the Ignite-0
ASIC.
The IGNITE project (INFN Ground-up INITiative-on micro-Electronics de-
velopments) aims to develop integrated micro-systems suitable for particle track-
ing in the next generation of high-luminosity experiment at the LHC. This ob-
jective involves the following system level requirements: a pixel pitch of ∼ 50
μm, a time resolution of at least 50 ps and a sustainable event rate up to 10
GHz/cm2. These specifications must be met within specific constraints: a ∼
1 W/cm2 power consumption, a radiation tolerance to TID up to 1 Grad, and
a material budget of 0.5 % Xo at most. The investigated system-level techno-
logical solutions include: a 28 nm CMOS front-end chip coupled with a silicon
3D sensor, a system assembly leveraging 3D integration technologies and an
integrated optical read-out.
Ignite-0 has been developed during 2023 in order to test individually the
building blocks for the future developments on the front-end ASIC. It contains
mainly the pixel front-end electronics such as the Analog Front-End (AFE) and
the TDC, but it also integrates various service blocks such as a Σ∆ DAC and
two different PLL architectures. All the integrated blocks have been designed
to satisfy the desired requirements and constraints both in terms of power,
performance and form-factor.
Both in terms of the AFE and the TDC, the implemented architectures
were developed on the basis of the ones of the Timespot1 front-end ASIC in
order to improve their performance and reliability. Moreover, six different AFE
architectures were investigated in order to test different combinations of the
preamplifier and discriminator.
This contribution will discuss the viability of the implemented solutions in
terms of their performance and robustness by comparing experimental results
and circuit simulations.
| Collaboration | IGNITE |
|---|---|
| Role of Submitter | I am the presenter |
