Speaker
Description
Monolithic active pixel sensors are considered for vertex or tracking detectors
of a large variety of particle physics experiments. Consequently, the design of
pixel matrices faces a wide range of specifications. That impacts in particular
the matrix read-out strategy, which is highly constrained in terms of power
consumption, layout area, time-stramping ability, and hit rate. Asynchronous
logic, an emerging ASIC design technique, seems promising in this respect, being
naturally data-driven and power-sparing.
We have developed a pixel matrix read-out architecture based on the local
interconnection of asynchronous N:1 arbiters with fixed priority. This architec-
ture is not limited by global signals and can achieve high bandwidth with a
fully column-parallel stream. Layouts of the required digital logic for a double
column were completed in the 65 nm CMOS imaging process currently explored
by the ALICE-ITS3 and CERN-EP R&D WP1.2 projects, for various combina-
tions of pixel pitch (18 to 30 μm), column depth (512 to 1024 pixels) and arbiter
size (2:1 to 1024:1).
This contribution presents the matrix read-out performances obtained from
post-layout simulations, assuming either a continuous hit-rate or hit bursts
clocked at 40 MHz, having in mind potential applications to HL-LHC experi-
ments (ALICE3 or LHCb phase 2 upgrade), Belle II long term upgrade and a
future high-energy leptonic collider like FCCee. Results explore the architecture
benefits in terms of area, power consumption, and timing. Especially we ad-
dress the feasibility of 18 μm pixel pitch with dissipation below 10 mW/cm2, the
maximum hit-rate allowing to time-stamp hits within 25 ns with an efficiency
of 99.9% and the evolution of the energy/hit/surface figure of merit with var-
ious configurations. Other aspects discussed include very small pitches (15μm
or less), the possibility of integrating such readout in a stitched sensor and a
discussion about radiation hardness.
| Role of Submitter | I am the presenter |
|---|
