Speaker
Description
The dual radiator RICH (dRICH) detector will be located in the hadron endcap of the ePIC experiment at the future Electron Ion Collider. The dRICH provides hadron identification from $\sim 3$ up to $\sim 50$ GeV/c thanks to two Cherenkov radiators and focusing mirrors. More than 300 thousand $3 \times 3$ mm$^2$ SiPMs are used as photosensors and the dRICH readout system is segmented into 1248 Photon Detection Units (PDU). Each PDU integrates in a modular fashion 256 SiPM photosensors with cooling and TDC readout electronics. The front-end electronics are based on four ALCOR ASICs, paired each to a matrix of 64 SiPMs, and an FPGA-based readout card (RDO). The ALCOR ASICs generate precise timestamp data, which are aggregated by the RDO card and streamed to the ePIC DAQ system via a 10 Gb/s optical link.
Given an expected radiation dose of $6\cdot10^{10}$ 1-MeV n$_\text{eq}/$cm$^2$, the detector performance is affected by an increase in dark count rate (DCR) of SiPM photosensors. Mitigation strategies, based on low-temperature operation and in-situ annealing, allow the DCR to be contained below 300 kHz after 200 fb$^{-1}$ of integrated luminosity. However, the dRICH system is expected to produce $\approx 7$ Tb/s when the DCR reaches 300 kHz, since it constitutes the dominant contribution of the data throughput. As the ePIC DAQ system can support a maximum throughput of $\approx 2$ Tb/s, we need to address the challenging data throughput with efficient online data-reduction techniques and a specific data-push readout architecture.
The dRICH-readout architecture will be presented, focusing mainly on the PDU front-end boards. A data reduction factor of five can be achieved by gating the data acquisition with the ALCOR shutter mode or by using external particle-tagger signals to separate DCR data from relevant data. Both these techniques are supported by data reduction at dRICH back-end level, based on neural-network architecture. The data reduction techniques will be introduced, highlighting the main role of the DAQ architecture design. First prototype PDU, including the RDO card and eight 32-channel ALCOR32 ASICs, will be presented. From a data-throughput perspective, results of prototype PDU, obtained using an IPbus-based readout system, will be compared to future studies exploiting the full bandwidth of the selected optical link.