Introductory course to VHDL and HLS FPGA programming

Sequential circuits in VHDL

24 Jun 2025, 14:30

2h

U6-11 (Università degli studi Milano Bicocca)

Hands on

Speaker

Andrea Triossi (Universita` degli Studi di Padova)

Description

Synchronous logic design. Inference in VHDL. State machines