Workshop on Electronics for Physics Experiments and Applications @INFN

5 Mar 2025, 10:00 → 7 Mar 2025, 16:00 Europe/Rome

Aula Magna Lingotto (Torino)

Il Workshop, promosso dalla Commissione Scientifica Nazionale 5 dedicata alla ricerca tecnologica e interdisciplinare, si propone di creare un'occasione di incontro e condivisione di idee tra utilizzatori e sviluppatori di tecnologie elettroniche per gli esperimenti di interesse dell’INFN.

Il workshop sarà organizzato nelle seguenti sessioni tematiche: 

Operatività in ambienti estremi: resistenza alle radiazioni, criogenia, basso  consumo, affidabilità.

Sfide di integrazione: acquisizione e trasmissione dati, scalabilità per grandi superfici e sistemi multi-canale, connessione sensore-ASIC, packaging, data processing con ASIC e FPGA.

Soluzioni per timing veloce e alta frequenza: tempo di volo, tracciamento di particelle, applicazioni deterministiche (sistemi di trigger e sincronizzazione), gestione di grandi volumi di dati, link ad alta velocità.

Prospettive future: elettronica per tecnologie quantistiche (rilevazione di singoli fotoni), rivelazione di onde gravitazionali (Einstein Telescope) e intelligenza artificiale real-time.

Al termine di ogni sessione una tavola rotonda guiderà la discussione.

Possono accedere all'evento solo le persone registrate. L'iscrizione è gratuita.

 

L'evento si svolgerà a Torino, nell'Aula Magna del Politecnico di Torino (Via Nizza 242) dal 5 al 7 marzo 2025.

La cena sociale sarà presso lo storico edificio della Società Canottieri Esperia, che ospita l’omonimo ristorante, a pochi passi dalla bellissima Piazza Vittorio Veneto.  

Ristorante ESPERIA - Corso Moncalieri 2, Torino.

 

Contribuiscono all'evento la CSN5, la Sezione di Torino dell'INFN, il Dipartimento di Fisica dell'Università e il Politecnico di Torino.

      

Si ringraziano per il contributo 

    

  

   

  

       

Convenzione-HotelPlaza.docx

Wednesday, 5 March

Welcome Greetings: Lunch, Institutional greetings and Introduction

1 Registration and Welcome lunch

2 Opening Remarks by Institutional Representatives

Alberto Quaranta, Marco Maggiora, Angelo Rivetti

Operation in extreme environment: Radiation hardness, cryogenics, ultra low power, reliability

Contributi su resistenza alle radiazioni, criogenia, power-spazio

3 Performance of nanoscale CMOS analog front-end circuits in extreme radiation environments

The next generation of silicon pixel detectors at high energy physics experiments sets unprecedented and extreme requirements to the microelectronic systems that are used to read out the sensors. Front-end integrated circuits will have to provide advanced analog and digital signal processing functions in high-density pixel readout cells, while handling huge data rates, operating at low power and standing extreme radiation levels. This talk is focused on the current effort to qualify advanced CMOS technology nodes (in particular the 28 nm one) and develop chip designs addressing the need for an adequate tolerance to ionizing radiation levels exceeding a total dose of 1 Grad. Analog functions such as signal amplification and discrimination are still crucial in these new designs, and the talk will discuss how analog performance of nanoscale CMOS circuits is affected by the operation in extreme radiation environments.

Speaker: Valerio Re

1 - Re - Performance of nanoscale CMOS analog front-end circuits in extreme radiation environments .pdf

4 Total Ionizing Dose effects at ultra high doses: a comparison between planar and FinFET technologies

In High-Energy physics applications, electronic devices will experience ever-increasing radiation doses. The forthcoming increase of the luminosity of the Large Hadron Collider (LHC) at CERN will require electronics to be able to withstand ultrahigh total ionizing dose (TID) levels up to 1 Grad(SiO2). For this reason, research on the TID response of modern technologies at ultrahigh doses has been receiving increasing attention in recent years in the HEP community. This paper reviews recent studies on TID effects on two modern commercial technologies: 28nm planar CMOS and 16nm FinFET technology. DC measurements provide insights into degradation mechanisms affecting oxide structures, including gate oxide, shallow trench isolation (STI), and spacers. The influence of transistor geometry and bias conditions during irradiation is analyzed, with emphasis on the mechanisms driving parameter degradation. Similarities and differences between the two technologies are highlighted.

Keywords: radiation effects; Total Ionizing Dose (TID); Metal–oxide semiconductor (MOS) transistors; FinFET

Speaker: Serena Mattiazzo (Università di Padova e INFN PD)

Mattiazzo_INFN_Workshop_Elettronica.pptx

5 Cold Electronics for Martian and Lunar Exploration. Threats, Opportunities and Technological Challenges

In recent years, lunar and Martian exploration have become more attractive to industries, with the prospect of a full-fledged lunar economy. Artemis and Mars sample return flagship missions are among the most significant, and the roadmap aims to define and design all the infrastructure needed for manned missions. To make this a reality, there is a strong need for robotic equipment (drills, rovers, manipulators) that will be required for in-situ resource utilization (ISRU) and to help humans survive. This spread of robotics involves several technological challenges related to hostile environments such as radiation and thermal conditions. In particular, the thermal range for Martian or lunar missions is roughly from -130°C to 120°C, with a number of cycles depending on the mission but typically ranging from 100 to 500. This will require robotic equipment to have dedicated thermal control systems to remain compatible with the electronics' nominal ranges. However, this is not always possible, as the thermal controls of various robotic systems may consequently demand excessive power budgets, which are not always compatible with the mission profile. Therefore, there is an area of research exploring the possibility of working with robotics and electronics that are compatible with such extreme temperature ranges. This work will present the methodology and results of Leonardo's expertise in this area, which may be valuable for the emerging lunar economy.

Speaker: Luca Zerilli

6 Radiation-hardened embedded FPGA for applications in high-energy physics

In future high-luminosity colliders, vertex detectors must withstand radiation levels of 6×10^16 neq/cm2 and a total ionization dose around 10 MGy on SiO2, while delivering an output bandwidth of approximately 100 Gbit/s per ASIC. To increase the active sensing area, these detectors will feature a three-dimensional design with Through Silicon Vias (TSVs) linking the frontend chip and an active interposer hosting the readout and data processing circuitry. Currently, frontend chips lack internal programmable logic, relegating data-processing tasks such as clustering and tracking to external commercial FPGAs.
The FERRad project addresses these limitations by developing highly integrated, radiation-hardened embedded FPGAs (eFPGAs) that can be integrated inside the active interposer. Its main deliverable is FERR1, a 28 nm ASIC embedding an eFPGA that tolerates up to 10 MGy total ionizing dose and is resilient to single event upsets.
This talk will present the FERRad project, detailing the development of FERR1, its architecture, radiation-hardening strategies, and preliminary performance assessments.

Speaker: Luca Frontini

4 - Frontini - .pdf

15:40 Coffee break

Operation in extreme environment: radiation hardness, cryogenics, ultra low power, reliability

Contributi su resistenza alle radiazioni, criogenia, power-spazio

7 Very low noise transimpedance amplifiers to readout SiPMs at cryogenic temperature

Several next-generation experiments will use SiPMs cooled to very low temperatures. The DUNE experiment will use large arrays of SiPMs to detect scintillation light produced in liquid argon (90 K) by neutrino interactions. Each channel will require single photon sensitivity with a total photosensitive area of tens of cm$^2$, read out with a single amplifier. Due to the low source impedance, with a total capacitance of 50-100 nF, an amplifier with very low voltage (series) noise is required, capable of operating reliably in liquid argon for decades of data acquisition, while consuming less than 1 mA per channel. The LHCb Upgrade II RICH detectors will use SiPMs to detect Cherenkov photons for particle identification. Due to the high neutron fluence, up to a few 10$^{13}$ cm$^{-2}$, cooling to low temperature, most likely to liquid nitrogen (77 K), will be the only way to ensure single photon sensitivity over the lifetime of the experiment. A time resolution of less than 100 ps RMS will be required, which in turn will require SiPMs to be characterised by an amplifier with very low voltage noise, wide bandwidth and low jitter. This talk will describe two transimpedance amplifier designs that meet the above requirements, both based on a SiGe HBT as the input device, followed by different operational amplifiers, both forming closed-loop configurations.

Speaker: Claudio Gotti (Istituto Nazionale di Fisica Nucleare)

Conf_20250305_SiPM_transimpedance.pdf

8 From lab to orbit: an overview of the IXPE readout electronics design

"The IXPE mission, featuring three x-ray telescopes with
polarization-sensitive Gas Pixel Detectors (GPD), aims to explore the
properties of cosmic x-ray sources in the 2 to 8 keV energy range. The
GPD and the readout electronics, developed at INFN, play a pivotal role
in capturing and processing the polarization data, which are central to
the mission's scientific objectives. We will explore the challenges and
solutions encountered during the development process, from laboratory
testing to deployment in orbit. The talk focuses on the architectural
and system design aspects, highlighting the communication interfaces,
sensor electronics, and the DAQ FPGA firmware design and verification
strategy employed to ensure the reliability and performance of these
critical components."

Speaker: Massimo Minuti (Istituto Nazionale di Fisica Nucleare)

6 - Minuti - From lab to orbit an overview of the IXPE readout electronics design.pdf

9 Low-Power Front-End Electronics chip design for the LITE_SLPD experiment

The LITE-SLPD (Lightweight Integrated Technology for Luminescence and Particle Detection) project explores the integration of advanced detection electronics within compact and low-power systems. As part of this effort, the GEN4 system introduces a fully integrated ASIC-based analog front-end for SiPM-based particle detection.
The ASIC chip, a key element of the GEN4 system, integrates core signal processing functionalities, including low-noise amplification, a fast discriminator, and a Peak & Hold circuit, previously implemented in discrete-component architectures. The front-end is designed using Second-Generation Current Conveyors (CCII+), optimized for reduced input impedance and enhanced recovery time, ensuring high-speed signal discrimination.
To support accurate circuit design and validation, a custom SiPM model has been developed in Cadence, reproducing realistic sensor behavior and facilitating front-end optimization. Simulations include transient response, AC analysis, and Monte Carlo evaluations of key circuit blocks, providing insight into performance variations across different conditions.
This talk will present the circuit architecture, highlighting key design choices such as the implementation of CCII+ structures with cascoded MOS stages, the biasing scheme and current-mode DAC, as well as the expected performance of the fast trigger generation and Peak & Hold response under increasing photon flux stimuli. Layout implementations and preliminary Monte Carlo results will also be discussed, outlining the next steps toward prototype realization.

Speaker: Davide Badoni (Istituto Nazionale di Fisica Nucleare)

Badoni_Davide.pdf

10 On-line Testing and Healing Permanent Radiation Effects in Reconfigurable Systems

Speaker: Luca Sterpone (Politecnico di Torino)

8 - Sterpone.pptx

11 Roundtable Discussion: Q&A and Insights

Thursday, 6 March

Integration challenges - 1: DAQ/Data Transmission/Scalability to large area and multi channels/ sensor-ASIC connection/ packaging/ ASIC/ FPGA data processing

chair: Lucio Pancheri, Roberto Amendola

12 The challenges of large ASIC integration and verification: the RD53 experience

Speaker: Flavio Loddo (Istituto Nazionale di Fisica Nucleare)

Loddo_INFN_WS_Mar2025.pdf

13 FEROCE and the journey of data from the detector to the computing farm

The growing demand for ever-larger datasets is a clear trend across nearly all areas of experimental physics. While computing power is essential for the processing farm responsible for handling these datasets, inefficient data movement can significantly undermine its effectiveness. Traditional networking stacks, responsible for managing network traffic, typically handle data via multiple copies, which results in expensive operations. A zero-copy networking approach can be achieved by integrating a remote direct memory access (RDMA) layer into the networking stack, offloading the processing workload to specialized hardware. FEROCE aims to enhance the conventional data acquisition system (DAQ) paradigm used in physics experiments by reducing the burden on back-end electronics. By adopting an efficient network protocol early in the data flow, the front-end electronics establish a direct link with the memory of DAQ computing nodes. Beyond the front-end, the entire DAQ system can be constructed solely from commercial off-the-shelf (COTS) hardware, leveraging the benefits of a widely adopted and well-established technology standard. FEROCE’s goal is to implement a lightweight version of the RoCEv2 stack on Field-Programmable Gate Array (FPGA), ensuring it is compatible with the size of the devices typically used in the front-end electronics of physics experiments. Additionally, it aims to include flash-based FPGA in the range of target devices, enabling deployment in radiation-intensive environments such as experimental halls in high-energy physics (HEP) experiments. The outcome of FEROCE is an FPGA core with a minimal resource footprint, capable of efficiently transmitting data buffers over a RoCEv2 network. The core has been designed to be as portable as possible, remaining vendor-agnostic for seamless integration into the front-end electronics of a wide variety of experiments. Its performance has been assessed within a network built on commodity hardware even in situations of traffic congestion.

Speaker: Andrea Triossi (Universita` degli Studi di Padova)

FEROCE_ws_grV.pdf

14 APE Router: an IP enabling low-latency packet communications for FPGA-based distributed processing.

The APE Router, developed by the INFN APE group, allows to implement a direct network for FPGA accelerators, enabling low-latency data transfer. This IP can be configured at design time for different environments, making it adaptable for applications ranging from embedded systems to large-scale HPC clusters and distributed FPGA-based systems.
Various applications will be presented, highlighting the APE Router’s ability to enable the development of scalable computing architectures.
A first use case is APEnet+, the high-performance low-latency interconnect system used in a hybrid CPU/GPU-based HPC platform.
The EURETILE project (EUropean REference TILed architecture Experiment) investigates and implements brain-inspired foundational innovations in the system architecture of massively parallel tiled computer architectures. In this project the APE Router, implemented in the DNP (Distributed Network Processor), manages all communication tasks, including deadlock-free routing, flow control, and integrity checks.
In the ExaNeSt project, focused on developing the interconnection network, storage, and cooling technologies required for exascale supercomputers, the APE Router aims to handle the communication between FPGAs in the basic compute node (QFDB) and between multiple QFDBs (intra-Mezzanine and inter-Mezzanine communications).
The EuroExa project, built on the results of ExaNeSt, aims to deliver an HPC platform using a modular integration approach to maximize cost-efficiency and scalability; the APE Router is used to connect computational nodes (CRDB) in a blade and to manage inter-blades connectivity.
Finally, the APE Router is the main component of the APEIRON framework, consisting of a generic architecture of an FPGA-based distributed stream processing system and the corresponding software stack.
One APEIRON application is partial particle identification on the stream of events generated by the RICH detector in the CERN NA62 experiment (FPGA RICH).
Additionally, APEIRON is used to implement a distributed ML model to discriminate between Noise Only and Signal + Noise events in the dRICH detector in the Epic experiment.

Speaker: Francesca Lo Cicero (Istituto Nazionale di Fisica Nucleare)

Lo_Cicero_APE_Router_2.pdf

15 The RETINA project: from R&D to integration in the DAQ of LHCb

The Artificial Retina is a computing architecture conceived for track reconstruction, particularly suitable for implementation on FPGAs. Its high throughput and low latency allow to integrate it into the readout of the DAQ system of a HEP experiment. The reconstructed tracks can be incorporated in the raw data as outputs from a virtual sub-detector.

After a decade of R&D, started with the INFN-CSN5 RETINA project, the LHCb collaboration decided to build a system based on this architecture to reconstruct tracks in the SciFi detector for Run 4: the downstream tracker (DWT).

This talk will review the key milestones achieved throughout the R&D program, from the first functional prototype developed during the RETINA project to the demonstrator processing live data coming from the LHCb monitoring farm during Run 3. It will continue with the description of the downstream tracker, how it will be integrated in the LHCb DAQ system, and the communication test between the two.

Speaker: Federico Lazzari (Istituto Nazionale di Fisica Nucleare)

CSN5_Retina_2025.pdf

10:35 Coffee break

Integration challenges - 2: DAQ/Data Transmission/Scalability to large area and multi channels/ sensor-ASIC connection/ packaging/ ASIC/ FPGA data processing

16 AI Engine Technology in AMD Devices

The AMD Versal™ adaptive SoCs combine programmable logic (PL), processing system (PS), and AI Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. A host of tools, software, libraries, IP, middleware, and frameworks enable Versal adaptive SoCs to support all industry-standard design flows.
AI Engines are an array of very-long instruction word (VLIW) processors with single instruction multiple data (SIMD) vector units that are highly optimized for compute-intensive applications, specifically digital signal processing (DSP), 5G wireless applications, and artificial intelligence (AI) technology such as machine learning (ML).
AI Engines are hardened blocks that provide multiple levels of parallelism including instruction-level and data-level parallelism. Instruction-level parallelism includes a scalar operation, up to two moves, two vector reads (loads), one vector write (store), and one vector instruction that can be executed—in total, a 7-way VLIW instruction per clock cycle. Data-level parallelism is achieved via vector-level operations where multiple sets of data can be operated on a per-clock-cycle basis. Each AI Engine contains both a vector and scalar processor, dedicated program memory, local data memory, and can access adjacent local memory in any of three neighboring directions. It also has access to DMA engines and AXI4 interconnect switches to communicate via streams to other AI Engines or to the programmable logic (PL) or the DMA.
The new AIE-ML block, is a variant of AI Engine block primarily targeted for machine learning inference applications, delivers one of the industry's best performance per Watt for a wide range of inference applications. 
As an application developer, it is possible to use one of the white box or black box flows for running a ML inference application on AIE-ML variants.
With the white box flow you can integrate custom kernels and dataflow graphs in the AI-ML variants C++ programming environment available within the AMD Vitis™ design flow.
A black box flow uses performance optimized Neural Processing Unit (NPU) IP from AMD to accelerate ML workloads in the AIE-ML variants. AMD Vitis™ AI is used as a front-end tool that parses the neural network graph, performs optimization, quantization of the graph, and generates compiled code that can be run on the AIE-ML variants hardware.
In the second part of the presentation we explore the integration of the AI Engine in Ryzen AI processors, highlighting the architecture and operation of the NPU. The NPU processing flow is described, from input reception to generating predictions, with autonomous access to DDR or HBM memory. Additionally, next-generation AI PC architectures are presented, featuring up to 12-core CPUs, advanced GPUs, and NPUs reaching 55 TOPS. The efficiency of the NPU is analyzed, showing up to a 31.6× performance improvement compared to the CPU and a significant reduction in power consumption. The section concludes with an overview of the unified AI software stack for Ryzen AI, ONNX model support, benchmarking tools, and a comparison between CPU and NPU efficiency.​

Speakers: Daniele Bagni, Giovanni Guasti

workshop INFN Torino_final.pptx

17 High speed serial links and radiation tolerant serdes devices for TTC distribution and DAQ in future HEP experiments

The increase of the luminosity in the upgrade of the Large Hadron Collider at CERN required the complete redesign of the Front-End electronics in most of the detectors of all the experiments. The first challenge was the increase of the data rates due to higher trigger rate and to the need of data from the Silicon Trackers for the generation of the level 1 trigger. The second challenge was the increase of the Total Ionizing Dose (up to 1Grad in the inner layers of the Silicon Trackers). New protocols for the distribution of the Timing, Trigger and Control (TTC) signals and for the data readout have been developed and implemented in radiation-tolerant IP-cores embedded in Front-End circuits. The technology scaling and the introduction of new design methodologies was the key for the success in the production of IP-cores that could fit the tight requirements w.r.t. performances and radiation tolerance. INFN designers have been deeply involved in these developments in the framework of different R&D projects supported by the Gr.5. A short survey of these projects is presented with a more detailed focus on the most recent results.

Speaker: Guido Magazzu' (Istituto Nazionale di Fisica Nucleare)

Serial_Links.pdf

18 ARCADIA FDMAPS development with LFoundry 110 nm CIS

In this contribution, a comprehensive overview of the development of FDMAPS in 110 nm CIS technology under the ARCADIA project will be presented.
After discussing the main activities and goals of the project, the design and characterization of sensors will be detailed, with special emphasis on three key points: (i) the Main Demonstrator, a 25-μm-pitch pixel array detector; (ii) the strip and pixel test structure, implemented for structure characterization and process qualification; (iii) and sensors with internal gain for timing applications.
Alongside laboratory and on-beam tests of already fabricated sensors, future perspectives in the area of 4D particle tracking for high-energy physics experiments will also be outlined, highlighting ongoing sensor development activities in view of near-future detectors at the FCC and Muon Collider.

Speaker: Marco Mandurrino (INFN, Sezione di Torino)

2025Mandurrino_WE.pdf

19 Roundtable Discussion: Q&A and Insights

13:00 Lunch

Solutions for fast timing and high frequency: ToF, particle tracking, deterministic applications (trigger systems-synchronization), large data throughput, high speed links)

Moderatori: Sara Garbolino, Gabriele Simi
Tavola Rotonda: Lino Demaria, Daniele Passeri, Sara Garbolino, Gabriele Simi

20 Sensors and electronics for extreme timing at extreme rates

High-Intensity 4D-tracking requires to match challenging requirements both in sensors and electronics development. The IGNITE project develops technical solutions for the next generation of trackers at colliders, planning to implement an integrated module, comprising sensor, electronics, and fast readout. System pixels are required to have pitch around 50 µm and time resolution below 30 ps.
The talk shows results on 3D silicon sensors concerning their performance in timing (10 ps) and radiation resistance (up to 10 18 n eq /cm 2 ). It also illustrates results about of a first-born prototype ASIC (Ignite0), which explores circuital solutions for Analog Front End and Time-to-Digital Converter circuits. After measurements, the AFE and TDC show time resolution around 20 ps rms. Such prototype structures have been tested before being integrated in a subsequent design, containing a 64x64 pixel matrix for the readout of pixelated sensors. We also present the design criteria (Fractal design) and expected performance of the Ignite64 ASIC, recently submitted for fabrication. Furthermore, specific strategies for a fully scalable design, up to 256x256 pixels, are illustrated and discussed.

Speakers: Adriano Lai, Adriano Lai (Istituto Nazionale di Fisica Nucleare)

ToWshop2025_ALai.pdf

21 Monolith Picosecond Avalanche Detector

Speaker: Thanushan Kugathasan

Thanushan.pdf

22 High resolution timing applications from the LGAD side

In a simplified view, the temporal resolution in LGAD can be considered the sum of two components: the jitter, linked to the electronics noise, and the Landau noise, related to non-uniform ionization. This contribution reviews how signal formation, charge drifts, and gain saturation determine the value of the Landau noise and impact the achievable time resolution. Implementing the above mechanisms in a simulation program allows the creation of libraries of signals that can be used to improve and validate front-end architectures and compare different designs. The talk will also review the front-end requirements of Resistive Silicon Detector (AC-and DC-coupled), detectors that require concurrent measurements of the ToA and amplitude, and the combination of signals from several electrodes.

Speaker: Nicolo Cartiglia

LGAD_Side.pptx

LGAD_Side_v3.pptx

23 Development of monolithic LGADs in 110nm CMOS: overview and perspectives

The stringent requirements for high-resolution Time-of-Flight detector layers in the HL-LHC experiments currently under design present significant detector development challenges. Achieving precise time resolution while balancing constraints on power consumption, material budget, fabrication, and assembly costs requires careful engineering trade-offs. Monolithic solutions offer a promising approach to addressing these challenges, driving increased R&D efforts to exploit impact ionization in monolithic detectors for precise timing and 4D tracking.
This contribution presents the development of Low-Gain Avalanche Detectors (LGADs) monolithically integrated into a customized 110nm CMOS process for the ALICE 3 detector. These sensors are based on modifications to the ARCADIA MAPS process, with a first test vehicle demonstrating both passive test devices and an active pixel matrix with integrated electronics. The key design modifications enabling LGAD functionality are critically examined, and future production plans and perspectives are discussed.

Speaker: Lucio Pancheri (University of Trento)

Pancheri_INFN_2025.pdf

15:40 Coffee break

Solutions for fast timing and high frequency: ToF, particle tracking, deterministic applications (trigger systems-synchronization), large data throughput, high speed links)

Moderatori: Sara Garbolino, Gabriele Simi
Tavola Rotonda: Lino Demaria, Daniele Passeri, Sara Garbolino, Gabriele Simi

24 A flexible electronics and DAQ system for the Timepix4 and Medipix4 ASICs

We present the development of a configurable data acquisition (DAQ) system for detectors integrating either the Timepix4 or Medipix4 ASIC as a front-end. These CMOS ASICs, developed by the CERN Medipix Collaboration, are designed for hybrid pixel detectors used in medical imaging and particle physics applications.

Our system is fully customizable, built on commercial hardware, and leverages standard communication protocols, ensuring high reusability across different projects. Customization is enabled through an open-source, fully configurable firmware and software stack.

The DAQ system is based on the AMD/Xilinx KCU105 development kit and utilizes a standard VITA 57.1 connector to interface with the detector. This setup ensures a reliable connection while maximizing the input bandwidth, reaching up to 80 Gbps from the ASICs. The system incorporates HDL-on-Git (HoG) features, facilitating flexible configuration of FPGA modules and allowing users to tailor peripheral integration. DAQ configuration is managed via a dedicated 1G Ethernet connection using the IPbus protocol. Additionally, customizable modules support fully configurable online data-reduction methods, with data readout handled via two 10G Ethernet connections implementing the downstream data path.

This approach presents several technical and distribution-level challenges, which will be explored in the presentation.

Speaker: Nicolò Vladi Biesuz (INFN, Ferrara (IT))

Slides_biesuz

25 The dRICH data acquisition system for ePIC: a general overview

The dual-radiator RICH (dRICH) detector of the ePIC experiment at the future Electron-Ion Collider (EIC) will use SiPMs for detecting Cherenkov light. The photodetector will cover a surface of ~3 m² with 3x3 mm² SiPMs, for a total of more than 300k channels to readout and will be the first application of SiPMs with single-photon detection in a high energy physics experiment.
We focus on the ePIC-dRICH data acquisition system starting from the ALCOR chip based front-end electronics up to the FELIX based DAQ system through the custom FPGA boards named RDO (Readout Data Output), which are currently being designed at INFN. A special section will also be dedicated to the DAQ prototypes that have been used up to now to readout 2048 SiPM sensors with particle beams at CERN-PS in May 2024.

Speaker: Davide Falchieri

falchieri_torino2025.pdf

26 Monolithic (ASPIDES) and hybrid (ADA_5D) approach to the readout of avalanche diodes in high dynamic range applications

The ASPIDES and ADA_5D projects, which deal with entirely different applications, calorimetry for particle physics on the one hand and cosmic ray atomic species identification in space-borne experiments on the other, rely upon two different approaches to tackle a shared problem: the need to process signals covering a large dynamic range.
ASPIDES aims at establishing a technology platform for the design, production and commissioning of monolithic Silicon Photomultipliers in CMOS technology, or digital SiPMs (dSiPMs), photon detectors with single-photon sensitivity and embedded functionalities. The presentation mostly focuses on the development of a fully digital SiPM for dual readout (DR) calorimetry applications, exploiting the intrinsically binary nature of single photon avalanche diodes (SPADs). The proposed device features a modular structure based on millimeter square sensors with integrated electronics, providing photon counting over a wide dynamic range, time tagging for the first photon arrival, threshold setting features for noise rejection, time of arrival of the last photon and the capability for disabling hot micro-cells. Fast photon counting is ensured through a parallel counter, based on adder trees and capable of reading out several thousands of micro-cells in a few nanoseconds. In wide dynamic range applications, like DR calorimetry, a fully digital approach brings about some definite advantages as compared to analog SiPMs, which are instead liable to random noise in the analog processing chain, fixed-pattern noise due to non uniformity among micro-cells and quantization noise in analog to digital conversion.
The ADA_5D collaboration is working on the design of a hybrid detector for spaceborne astrophysics experiments. The elementary detector module is based on four low gain avalanche detectors (LGADs) bonded to and read out by a four-channel processing chip in CMOS technology, gathering 5-dimensional (5D) information from the interaction with cosmic ray (CR) particles: position (X, Y and Z coordinates in a multiple layer configuration), atomic number and time of arrival. The underlying idea is to use time of flight (ToF) measurements to reject back scattered radiation from the on-board calorimeter and improve charge resolution in the identification of CR elements. The individual readout channel consists of two branches, departing from a two-stage analog processor which includes a charge sensitive amplifier (CSA) with rail-to-rail output and dynamic signal compression followed by a CR-RC shaper with selectable peaking times, from 10 to 45 ns. The solution adopted for the design of the CSA, featuring a tri-linear input-output trans-characteristic, is instrumental in maintaining a signal-to-noise ratio in excess of 200 over the entire dynamic range of the input signal, covering more than three decades in charge. One of the two abovementioned branches is used for signal timing and includes a comparator and a time-to-amplitude converter. The second branch is devoted to amplitude measurement and consists of a peak stretcher. In an elementary readout chip, consisting as already mentioned of four of the above described channels, an incremental ADC is used for analog to digital conversion of timing and amplitude measurements (8 samples overall) through a multiplexer.
The talk describes and discusses the solutions proposed for the readout electronics in the ASPIDES and ADA_5D projects, with emphasis on the potential advancements with respect to the state of the art.

Speaker: Lodovico Ratti

electronics_workshop_ratti.pdf

27 New ASICs for medical imaging with embedded machine learning capability

Recent generations of ASICs developed at Polimi for medical imaging applications will be presented. ASICs for SiPMs readout of monolithic scintillators allow spectroscopy and position of interaction measurements of gamma-rays, also within a large dynamic range thanks to an active gain control mechanism in the analog channel. Such ASICs are applied, in particular, in prompt-gamma measurements for dose verification in particle therapy. The new ANNA ASIC implements an integrated neural network which processes directly the analog signals from the detectors, towards an on-chip reconstruction of the gamma-ray position of interaction in the scintillator.

Speaker: Carlo Ettore Nicola Fiorini (Istituto Nazionale di Fisica Nucleare)

Fiorini Workshop Electronics 06-03-25.pdf

28 Roundtable Discussion: Q&A and Insight

Social dinner

Friday, 7 March

Future (Electronics for Quantum Technologies (Single Photon Detection), gravitational wave detection (Einstein Telescope), and Real-Time Artificial Intelligence

29 Electronic System for the Control and Readout of Superconducting Quantum Bits

Superconducting qubits are among the most promising platforms for quantum computing and quantum sensing, requiring advanced electronic systems for their control and readout. These systems must generate high-fidelity microwave pulses, ensure low-noise amplification, and enable fast, high-precision measurements. The control system relies on arbitrary waveform generators (AWGs) and microwave sources to produce tailored pulse sequences for quantum gate operations. The readout system must efficiently extract quantum state information while minimizing decoherence and measurement-induced backaction. This is typically achieved through dispersive readout schemes, leveraging high-electron-mobility transistor (HEMT) amplifiers at cryogenic temperatures. A key aspect of modern quantum electronics is the integration of control and readout functionalities into programmable hardware. Platforms such as RF system-on-chip (RFSoC) devices offer a powerful solution by combining fast digital-to-analog and analog-to-digital converters (DACs/ADCs) with real-time signal processing capabilities. These allow for low-latency feedback, real-time calibration, and efficient multiplexed readout, essential for scaling up quantum processors.

Beyond computing applications, superconducting qubits are also being explored within INFN projects for fundamental physics, including quantum sensing for light dark matter and radiation detection and quantum simulation of many-body systems. These applications push the limits of current electronic architectures, requiring optimized solutions for scalability and integration. In this talk, I will present an overview of the electronic architecture required to operate superconducting qubits, focusing on both control and readout aspects.

Speaker: Dr Andrea Giachero (INFN Milano-Bicocca)

giachero.ElecINFN2025.pdf

30 Simultaneous control and readout of multiple superconducting qubits

Superconducting quantum bits, or qubits, are among the most promising technologies for the realization of fully-functioning quantum computers, and their possible applications, ranging from quantum simulations to quantum sensing and particle detection, make these devices a potentially interesting tool also for particle physics experiments.
A fundamental step in the research on this field has been the development of a reliable technology for the manipulation and readout of qubit states. Over the past years, results on single-qubit measurements have improved dramatically, with experiments that reached readout fidelities exceeding 99.5% in some devices. Though, in order to unlock the full potential of quantum devices, the same results need to be achieved also in control and readout systems capable of simultaneously operating multiple qubits.
In this talk I will illustrate a system for the readout and control of superconducting qubits capable of probing simultaneously multiple qubits. The system relies on RFSoC boards for the production and the readout of the RF pulses used for the measurement and can probe simultaneously up to four qubits, with the possibility to scale to a higher number of qubits.

Speaker: Francesco De Dominicis (Istituto Nazionale di Fisica Nucleare)

Slides_DeDominicis.pdf

31 CMOS SPAD Arrays for Quantum Imaging: Opportunities and Challenges

Quantum imaging is an emerging field that leverages the principles of quantum mechanics to achieve imaging capabilities beyond classical limits. By exploiting entangled photon, quantum imaging techniques enable enhanced resolution, improved sensitivity, and novel imaging modalities such as super-resolution, ghost imaging, sub-shot-noise imaging. These approaches hold significant promise for applications in biomedical imaging, remote sensing, and optical metrology.
In this context, Single-Photon Avalanche Diode (SPAD) arrays in CMOS technology play a crucial role in the advancement of quantum imaging technologies. These arrays integrate multiple highly sensitive photodetectors capable of detecting individual photons. Thanks to custom in-pixel electronics, they can perform various operations such as photon time-stamping (with a precision in the order of hundreds of picoseconds), photon counting, time-gating and others. Combined with their capabilities for high-speed image acquisition, photon-number resolving, and spatially resolved measurements, SPAD arrays are ideal for quantum imaging experiments.
Two SPAD arrays designed in 110 nm CIS FSI technology will be presented in this work, each designed for different quantum imaging applications. The first is a multi-purpose 224×272 SPAD array with a pixel pitch of 30 µm and a fill-factor of 12.9%, featuring reconfigurable in-pixel logic. This allows the SPAD array to adapt to different quantum imaging experiments , performing photon timestamping with an in-pixel Time-to-Digital converter with a timing resolution of 180 ps, photon counting up to 127 events per pixel, and other functionalities. These capabilities make it particularly suitable for super-resolution imaging.
The second 472×456 SPAD array is specifically designed for quantum ghost imaging, exploiting entangled photon pairs properties to reconstruct high-quality images in the infrared portion of the spectrum domain. A 17 µm pixel pitch with up to 31% fill-factor implements an in-pixel backward-looking temporal correlation logic to spatially resolve entangled photons in a ghost imaging setup. Time correlation is performed between the photon and an external trigger directly at pixel level, by employing an asynchronous delay mechanism combined with a tunable time correlation window . The SPAD array allows tuning of the pixel’s correlation window width and delay, ranging from 2 ns to 27 ns and from 5 ns to 40 ns, respectively. An integrated address-based event readout circuit enables reading out only the pixels that record a correlation, significantly reducing power consumption and overall acquisition time for ghost imaging by more than an order of magnitude compared to conventional setups.
These developments demonstrate the versatility and potential of SPAD technology in pushing the boundaries of quantum imaging.

Speaker: Massimo Gandola (Fondazione Bruno Kessler)

INFN_QI_07_03_2025_upload.pptx

32 Random Power, a platform of random bit streamers: challenges in its ASIC implementation and envisaged solutions

Random Power is an innovation project turned into a start-up company, developing a platform of random bit streamers based on quantum tunneling in Silicon Devices. The patent protected principle has been implemented in a series of boards and in an ASIC, currently in its final assessment phase. The basic building blocks to make it compliant to the FIPS-140-3 certification protocol, together with critical functionality details and architectural solutions will be presented, with a focus on security issues to be guaranteed aling with testability and redundancy.

Speaker: Massimo Caccia (Istituto Nazionale di Fisica Nucleare)

10:20 Coffee break

Future (Electronics for Quantum Technologies (Single Photon Detection), gravitational wave detection (Einstein Telescope), and Real-Time Artificial Intelligence

33 Next-Generation Control Systems for European Gravitational Waves Detectors

Speaker: Alberto Gennai (Istituto Nazionale di Fisica Nucleare)

GennaiTorinoWS (1).pdf

34 Low Latency Data Acquisition for Future Gravitational Waves Detectors

Future gravitational wave detectors will require increasingly sophisticated control systems to enhance sensitivity and expand operational range. A key challenge is optimizing the entire data acquisition and processing loop, from ADC conversion to real-time elaboration and DAC actuation, where low, deterministic latency is essential for improving overall system performance and extending control bandwidth. In this talk, we will present our efforts to address this challenge, focusing on the integration of FPGA-based solutions to enable high-bandwidth data handling and improve system flexibility. We will discuss the development of a custom board based on Ultrascale FPGAs, along with advanced interfaces enabling fast and efficient data conversion and transfer to powerful real-time processing cores and DAQ units. This solution integrates high-speed ADC/DAC interfaces, using low-latency communication protocols like JESD204, and incorporates advanced data transfer mechanisms toward DSP or GPU based processors. In particular, in the view of using GPUs, a significant effort is dedicated on overcoming the limitations of traditional PCIe transactions, leveraging hardware accelerators and direct memory access techniques to optimize data flow. These developments provide a strong foundation for next-generation control architectures, with the potential to integrate machine learning techniques to further enhance adaptability and performance.

Speaker: Paolo Prosperi (Istituto Nazionale di Fisica Nucleare)

ProsperiWorkshopElettronicaTorino.pdf

35 Memristor-CMOS Synergy – Innovating Circuit Configurations for In-memory Computing

Memristors, first theorized by Leon Chua in 1971 as the fourth fundamental circuit element, were experimentally realized in 2008 by researchers at HP Labs. Since then, significant progress has been made in the development of memristive devices, unlocking new opportunities for energy-efficient computing and high-density memory storage. While companies such as Knowm focus on research-driven memristor technologies, particularly in neuromorphic computing, others like Fujitsu have successfully integrated memristors into commercial ReRAM products, demonstrating their potential as viable non-volatile memory solutions. Meanwhile, companies such as Weebit are working on providing intellectual property (IP) for memristor-based structures, including memory arrays and devices compatible with CMOS technology.

The MEMPHYS project explores the integration of memristors with CMOS technology to innovate circuit architectures for in-memory computing, particularly in high-energy physics (HEP) experiments. As traditional CMOS-based trigger and data acquisition (DAQ) systems face growing challenges in power efficiency, latency, and scalability—especially in high-radiation, high-data-rate environments—MEMPHYS investigates the feasibility of memristor-based neuromorphic processing for real-time event selection directly on analog detector signals. This approach could significantly reduce data transmission bottlenecks while improving energy efficiency.

Furthermore, the project examines ReRAM-based architectures as a promising radiation-tolerant solution to enhance the reliability and reconfigurability of field-programmable gate arrays (FPGAs), essential components in modern DAQ systems. By leveraging the low-power and non-volatile nature of memristors, this research aims to develop next-generation computing paradigms. The experimental validation focuses on assessing radiation hardness, operational stability, and scalability under real-world HEP conditions. Beyond particle physics, these advancements could have broader applications in medical imaging, space instrumentation, and neuromorphic computing.

Speaker: Valerio Bocci (Istituto Nazionale di Fisica Nucleare)

Torino memristor_VBocci_c.pdf

36 Exploring Novel Neuromorphic Computing Architectures with a Multi-Node FPGA System

Keywords: Neuromorphic-Computing, spiking neural network, computational neuroscience, HPC, Edge Computing

Brain-inspired Spiking Neural Networks represent a promising frontier in computational models, offering potential advantages over traditional computing paradigms in terms of energy efficiency, temporal information processing, and adaptability to dynamic data. This can benefit numerous applications, such as real-time signal processing and pattern recognition in resource-constrained environments. The research landscape in neuromorphic computing, which encompasses hardware architectures designed to efficiently implement these biologically-inspired networks, is highly heterogeneous, with diverse approaches balancing biological plausibility against computational efficiency. In this diversity there is significant opportunity for exploration of novel architecture designs and applications.

This presentation introduces our work on a new multi-core neuromorphic architecture prototype that is under development within the INFN Brainstain project, where we have brought together the diverse expertise present inside CSN5, from the design and implementation of high performance computing architectures dedicated to physics tasks, to the modeling of novel neuron models that enable incremental learning through efficient integration of contextual and sensory information and the mechanism of apical amplification.

Leveraging on the proprietary APEIRON framework for flexible, low latency communication we aim to deploy our architecture prototype on a multi-FPGA system. We adopt a software-hardware codesign workflow that relies on early validation through a high level simulator of the architecture, and on the High Level Synthesis (HLS) programming paradigm for translation to a hardware implementation, for relatively fast and simple reprogramming, debugging and feature enhancements. The flexibility of this approach and the modular design of our architecture will allow us to explore support for different models of neuron dynamics, such as multi-compartment neuron models, and study the system performance with different inter-core communication schemes, such as specialized broadcast or multicast algorithms.

This presentation will discuss our architectural approach, the features and capabilities planned for the system, it will describe the current status of development, and it will outline the future direction of the project.

Speaker: Pierpaolo Perticaroli (Istituto Nazionale di Fisica Nucleare)

Perticaroli_Exploring_novel_neuromorphic_1.pdf

Roundtable and Closing Remarks

13:00 Lunch