SVT - FE chip

Friday 4 Nov 2011, 09:00 → 11:00 Europe/Rome

Giuliana Rizzo (PI)

EVO Connection Title: SVT-FE chip Description: Community: SuperB Password: supersvt Meeting Access Information: - Meeting URL http://evo.caltech.edu/evoNext/koala.jnlp?meeting=MeMMMu2v2uD2DB9a9sDv9e - Password: supersvt - Phone Bridge ID: 425 2359 Password: 1229 Central European Time (+0100) Start 2011-11-04 09:00 End 2011-11-04 11:00 In case EVO doesn't work we will use the INFN Phone system: http://server10.infn.it/video/index.php?page=telephone_numbers - Dial code 3232 #

09:00 → 09:15 Update on in-strip logic design

Speaker: Roberto Beccherle (GE)

09:15 → 09:30 Update on readout architecture VHDL simulation

Speaker: Filippo Maria Giorgi (BO)

09:30 → 09:45 Update on analog design for fast channels L0-L3

Speaker: Lodovico Ratti (PV)

09:45 → 10:00 Peripheral blocks

Speaker: Valerio Re (PV)

10:00 → 10:15 Update on analog design for L4-L5

Speaker: Carlo Ettore Fiorini (MI)

Slides FE_Polimi_04-11-11.pptx

10:15 → 11:00 Discussion