SVT - FE chip (4 November 2011) · Agenda (Indico)

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SVT - FE chip

Friday 4 November 2011 - 09:00

Monday 31 October 2011
Tuesday 1 November 2011
Wednesday 2 November 2011
Thursday 3 November 2011
Friday 4 November 2011
09:00 Update on in-strip logic design - Roberto Beccherle (GE)
Update on in-strip logic design
- Roberto Beccherle (GE)
09:00 - 09:15
09:15 Update on readout architecture VHDL simulation - Filippo Maria Giorgi (BO)
Update on readout architecture VHDL simulation
- Filippo Maria Giorgi (BO)
09:15 - 09:30
09:30 Update on analog design for fast channels L0-L3 - Lodovico Ratti (PV)
Update on analog design for fast channels L0-L3
- Lodovico Ratti (PV)
09:30 - 09:45
09:45 Peripheral blocks - Valerio Re (PV)
Peripheral blocks
- Valerio Re (PV)
09:45 - 10:00
10:00 Update on analog design for L4-L5 - Carlo Ettore Fiorini (MI)
Update on analog design for L4-L5
- Carlo Ettore Fiorini (MI)
10:00 - 10:15
10:15 Discussion
Discussion
10:15 - 11:00

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