28–30 Oct 2024
INFN Frascati National Laboratories
Europe/Rome timezone

Integration of a Digital PLL in LLRF Systems for Advanced Cavity Characterization

29 Oct 2024, 16:40
1h 50m
Bldg. 36 Bruno Touschek Auditorium

Bldg. 36 Bruno Touschek Auditorium

Poster Measurement and calibration Poster Session II (Measurement and calibration)

Speakers

Juan Salvador Fernández Prat (Safran Electronic & Defense Spain S. L.) Javier Benavides Caro (Safran Electronic & Defense S.L.)

Description

The Low-Level Radio Frequency (LLRF) system is a vital subsystem in particle accelerator facilities, tasked with generating and maintaining a stable electric field within accelerator cavities by precisely controlling both amplitude and phase. As facilities transition from legacy analogue LLRF systems to modern digital counterparts, the enhanced computational power of current Field-Programmable Gate Arrays (FPGAs) presents opportunities to introduce new, sophisticated functionalities.

In this work, we explore the design and implementation of a fully digital Phase-Locked Loop (PLL) integrated within the LLRF system. This digital PLL is capable of automatically tracking the resonant frequency of the accelerator cavities, ensuring that the system continuously adapts to any deviations from the nominal resonant frequency. Moreover, this feature extends beyond simple frequency monitoring; it can also be leveraged for detailed characterization of the magnitude response of the cavity.

The implementation details and performance evaluation of this digital PLL feature will be thoroughly discussed in this work.

Primary authors

Juan Salvador Fernández Prat (Safran Electronic & Defense Spain S. L.) Javier Benavides Caro (Safran Electronic & Defense S.L.)

Presentation materials