Speaker
Dr
Davide Badoni
(I.N.F.N. Roma Tor Vergata)
Description
We have designed and realised a Front-End chip for MPPC in standard CMOS 0.35$\mu$m technology. The channel presents a low input impedance in order to reduce as much as possible the recovery time of the sensor. This is achieved using the current domain for processing signals through the current conveyors (CCII) as building blocks of the channel. A current feed-back with low-pass filter has also been used to realise a sensitive improvement of the pile-up problem, in case of high repetition rate events. An independent arming threshold is available for each channel, providing the selection of the event through the peak level (proportional to the number of simultaneously hit pixels) reached by the signal. A constant-fraction functionality is present in order to reduce the well know time-walk problem. The delay in the correspondent branch is obtained by using an additional CCII block. The channel is also equipped with analog output and integrated analog output. The digital output of the discriminator channel has adjustable time width. The pilot chip is made up of five channels. All the values of the independent thresholds are stored in 10-bit registers as well as the the values of the trigger output width and the main polarisation current of the CCII blocks. All the registers are writable from a standard three-wire SPI. These features make the chip fully self-consistent. In this work we present and discuss the simulation results together with the preliminary test performed.
Primary author
Dr
Davide Badoni
(I.N.F.N. Roma Tor Vergata)
Co-authors
Dr
Dario Moricciani
(I.N.F.N. Roma Tor Vergata)
Dr
Francesco Gonnella
(I.N.F.N. L.N.F.)
Prof.
Roberto Messi
(I.N.F.N. Roma Tor Vergata)
