Speaker
Aurora Pepino
(INFN - Lecce)
Description
A fast readout algorithm for Cluster Counting and Timing purposes has been implemented and tested on a Virtex 6 core FPGA board. The algorithm analyzes and stores data coming from Helium based drift tube instrumented with a 1 GSa/s ADC and represents the outcome of balancing between efficiency and high speed performance, resulting in high efficiency peak data extraction on simulated signals as well as on experimental ones.
A relative efficiency evaluation with respect to commercial sophisticated peak finding software (i.e. PeakFit) will be reported.
Based on these results, the developed algorithm could be adopted in order to build an electronics VME board serving multiple fADC channels and be used as an on-line preprocessing stage for signals coming from drift chambers making use of Cluster Counting/Timing techniques.
Primary authors
Aurora Pepino
(INFN - Lecce)
Dr
Francesco Grancagnolo
(INFN Sezione di Lecce)
Dr
Giovanni Francesco Tassielli
(Università Marconi Roma & INFN Lecce)
Dr
Luigi Cappelli
(Università di Cassino & INFN Lecce)
Dr
Pietro Creti
(INFN Sezione di Lecce)
