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TREDI 2024

20–22 Feb 2024
Physics Dpt
Europe/Rome timezone

Simona Bortot

Session

Electronics

E1
20 Feb 2024, 16:30
Aula Magna (Physics Dpt)

Aula Magna

Physics Dpt

Via Pietro Giuria 1

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  1. 18. Test results of the monolithic ASIC for the upgraded preshower detector of the FASER experiment at the LHC
    Chiara Magliocca
    20/02/2024, 16:30

    The FASER experiment at the Large Hadron Collider (LHC) aims to detect new, long-lived fundamental particles and to study neutrino interactions. To enhance its discovery potential, a W-Si preshower detector is being built, targeting surface commissioning and then installation during the second half of 2024. The new preshower will enable the identification and reconstruction of electromagnetic...

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  2. 8. The ASIC FAST3, a front-end integrated circuit optimized to read out 50 µm LGAD sensors
    Marco Ferrero (Istituto Nazionale di Fisica Nucleare)
    20/02/2024, 16:50

    In this contribution, we will present the very preliminary experimental performances obtained with the ASIC FAST3. FAST3 is a multi-channel amplifier optimized to read out LGAD sensors and designed to achieve a temporal jitter below 20 ps.
    FAST3 was developed by the microelectronic group of INFN Turin. FAST3 has been designed in UMC 110 nm CMOS technology, and has 16 channels distributed over...

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  3. 27. ToASt : a 64-channel ASIC for the readout of the Silicon Strip Detectors of the PANDA experiment
    Giovanni Mazza (Istituto Nazionale di Fisica Nucleare)
    20/02/2024, 17:10

    The design of the Micro Vertex Detector (MVD) for the PANDA experiment is optimized for the detection of secondary vertices and maximum acceptance close to the interaction point. The MVD consists of a 4-layer barrel section, placed around the interaction point, and a 6-disks forward section, located in the forward position. The outermost layers of the MVD will be equipped with double sided...

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  4. 29. Tests and Characterization of ASTRA-64 ASIC for Silicon Micro-Strip Detectors Read-Out
    Mattia Barbanera (Istituto Nazionale di Fisica Nucleare)
    20/02/2024, 17:30

    ASTRA-64 (Adaptable Silicon sTrip Read-out ASIC) is a 64-channel mixed-signal custom IC designed for micro-strip silicon sensors read-out. Manufactured in a 110-nm technology node, it comprises two identical mirrored subcircuits, each accommodating 32 channels.
    Recursively, each channel integrates two main blocks: a charge-sensitive amplifier and a shaper. The former features two programmable...

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