20–22 Feb 2024
Physics Dpt
Europe/Rome timezone

The ASIC FAST3, a front-end integrated circuit optimized to read out 50 µm LGAD sensors

20 Feb 2024, 16:50
20m
Aula Magna (Physics Dpt)

Aula Magna

Physics Dpt

Via Pietro Giuria 1

Speaker

Marco Ferrero (Istituto Nazionale di Fisica Nucleare)

Description

In this contribution, we will present the very preliminary experimental performances obtained with the ASIC FAST3. FAST3 is a multi-channel amplifier optimized to read out LGAD sensors and designed to achieve a temporal jitter below 20 ps.
FAST3 was developed by the microelectronic group of INFN Turin. FAST3 has been designed in UMC 110 nm CMOS technology, and has 16 channels distributed over a surface of 1x5 mm2; the power rail is 1.2 V and the expected power consumption is 2.4 mW/ch. Each FAST3 readout channel presents an amplifier with low input impedance (<50 Ohm), and wide bandwidth (~ 1 GHz) and wide input range in terms of charge (3-40 fC).
The experimental tests presented include i) charge injection through an external pulser, in order to evaluate the temporal jitter of the ASIC as a function of the injected charge; ii) the characterization of the temporal performances of the ASIC coupled with an LGAD sensor 50µm thick, using a Sr90 beta source to generate non-uniform signals inside the LGAD.

Primary author

Marco Ferrero (Istituto Nazionale di Fisica Nucleare)

Co-authors

Cecilia Hanna (Istituto Nazionale di Fisica Nucleare) Federico Siviero (Istituto Nazionale di Fisica Nucleare) Leonardo Lanteri (Istituto Nazionale di Fisica Nucleare) Luca Menzio (Istituto Nazionale di Fisica Nucleare) Nicolo' Cartiglia (Istituto Nazionale di Fisica Nucleare) Robert Stephen White Roberta Arcidiacono (Istituto Nazionale di Fisica Nucleare) Roberto Mulargia (Istituto Nazionale di Fisica Nucleare) Valentina Sola (Istituto Nazionale di Fisica Nucleare)

Presentation materials