Speaker
Description
The High-Luminosity Large Hadron Collider (HL-LHC) project aims to boost the performance of the LHC, augmenting the potential for discoveries and the accuracy of SM measurements. From the LHC Run-4 onwards, the upgrade aims at increasing the instantaneous luminosity of the machine, to target an overall ten-fold increase of the collected dataset compared to the LHC initial design. In order to withstand the expected increase of both integrated doses and event rates, the on-board electronics hosting the first level of readout and trigger of the CMS DT Chambers will be replaced with the new On-Board electronics for DT (OBDT). Time digitization (TDC) data from the OBDTs will be streamed directly to an upgraded backend system that, relying on the latest commercial FPGAs, will perform event building and generate trigger primitives (TP) exploiting the ultimate DT cell resolution. Additionally, the Detector Safety System (DSS) will also undergo a redesign, which entails the development of a new hardware, called MONitor for SAfety (Monsa) system. To demonstrate the Phase-2 architecture, a readout based on early OBDT prototypes was deployed in parallel to the legacy electronics through front-end splitting on a full DT sector. Data from the OBDTs is streamed into proxy backend boards, where the trigger primitive generation algorithm designed for the upgrade is run. In parallel, close-to final prototypes of the OBDTs were assembled and test under radiation. In this report, the motivation for such an upgrade will be highlighted and the status of the development and testing of the DT Phase-2 electronics at large will be discussed. Moreover, the most up to date performance results from the DT slice-test operation will be presented, as well as the plans to augment the demonstrator using final OBDT prototypes.
| In-person participation | Yes |
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