28th RD50 Workshop (Torino)

Session

Sensor Design

6 Jun 2016, 14:00

Aula Magna della Cavallerizza Reale (Torino)

Conveners

Sensor Design

• Daniela Bortoletto (Purdue University)

13. The influence of edge effects on the determination of doping profiles using silicon pad diodes

Dr Eckhart Fretwurst (University of Hamburg)

06/06/2016, 14:00

Edge effects for square p+n pad diodes with guard rings, fabricated on high-ohmic silicon, are investigated. Using capacitance-voltage measurements of two pad p+n diodes with different areas, the planar and the edge contributions to the diode capacitance are determined separately. Different methods of extracting the doping concentration are compared. In practically all cases it is found that...

24. Test beam and clean room studies of ATLAS PPS modules with alternative bias rail geometries

Dr Clara Nellist (LAL, Orsay)

06/06/2016, 14:20

It is known that for the current design of planar pixel sensors, there is a drop of efficiency at the punch-through structure of the biasing system at the edge of pixels. Various geometries, as part of the ATLAS Inner Tracker (ITK) upgrade, are being investigated to reduce this inefficiency. Planar pixel sensors with multiple alternative bias rail geometries have been tested at the SPS beam...

8. Status of the RD50-Project "NitroStrip"

Alexander Dierlamm (Karlsruhe Institute of Technology)

06/06/2016, 14:40

The aim of the "NitroStrip" project is to extent the "NitroSil" project by preforming charge collection measurements on strip sensors, which are not included in "NitroSil". Both projects evaluate the radiation resistance of nitrogen enriched silicon. We will present the finally approved project plan and the current status of the project.

9. Performance of thin n-in-p planar pixel modules with and without active edge

Ms Natascha Savic (Max-Planck-Institute for Physics)

06/06/2016, 15:00

New productions of thin n-in-p pixel sensors designed at MPP will be presented. Sensors of thicknesses of 100 and 150 um have been produced at ADVACAM and CiS and interconnected to FE-I4 chips. At ADVACAM SOI wafers were employed, while at CiS anisotropic KOH etching was carried out to create backside cavities in the wafer leaving thicker frames around each single structure. To maximize the...