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Seminars and Colloquia
The FP7-IAPP-FTK project: real-time image reconstruction for Hadron Collider experiments and a possible application to the A.I. field
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Europe/Rome
131 (INFN edificio C)
131
INFN edificio C
Description
I present the architecture and the performances of an ultra-fast and compact processor, Fast Tracker, developed for high-quality image processing in the Hadron Collider’s triggers.
The proposed hardware, optimized for pattern recognition, data reduction, and fast information extraction, is based on cooperating full-custom ASICs named Associative Memories. The Associative Memory chip is suitable for massive parallelism in data correlation searches and it is the most ingenious piece of the entire system. It takes full advantage of the intrinsic parallel nature of the combinatorial problem by comparing at once the image under analysis to a set of pre-calculated "expectations", or patterns. This approach reduces to linear the exponential complexity of CPU-based algorithms and the problem is solved by the time data are loaded into the chip.
We claim that the Associative Memory-based processor can simulate the preliminary image processing stages performed by the brain, such as the identification of shape edges. In fact, the Associative Memory pattern matching can implement fast pattern selection/filtering of the type studied in some models of human vision. We pursue the conjecture [1] that the brain works by dramatically reducing the input information; it would select, for higher-level processing, only the input data that match a set of predetermined patterns.
Our current goal consists in the hardware implementation of an Associative Memory-based processor for real-time extraction of the most relevant features from static and non-static images. We present here the Associative Memory architecture and some simulation studies that show the Associative Memory potentialities in edge detection [1].
A single Associative Memory chip could operate at low consumption in embedded systems, while an array of ~hundred chips could implement a pre-processor for moving image analyses.
[1] Del Viva M.M., Punzi G., Benedetti D, "Information and Perception of Meaningful Patterns", PLoS ONE 8(7): e69154. doi:10.1371/journal.pone.006915