Speaker
Description
Monolithic Active Pixel Sensors (MAPS) have become central to modern vertexing and tracking detectors, but forthcoming facilities such as the FCC-ee will demand unprecedented power efficiency, timing precision, and bandwidth. At Brookhaven National Laboratory we are advancing several complementary innovations that collectively define the next generation of MAPS.
At the front end, we have developed a 0.5 V charge-sensitive amplifier–discriminator chain using self-cascoded transistors with pole–zero cancellation. This approach multiplies the collected charge before voltage conversion, achieving sensitivities on the order of 1 mV/e⁻ while operating below 100 nA bias currents—an enabling feature for thin, small-footprint pixels .
To eliminate frame-based dead time and reduce dynamic power, we introduced EDWARD (Event-Driven With Access and Reset Decoder), a fully asynchronous, fair-arbitration binary tree that guarantees gap-free event delivery with sub-microsecond latency. Prototypes in 65 nm CMOS demonstrated sustained MHz-scale single-photon imaging while maintaining compatibility with synchronous DAQ .
For wafer-scale stitched MAPS, high-speed data movement is addressed by the Backbone Transmission Line Encoding (BTLE) driver, which employs digital duobinary coding and FIR-based pulse shaping to enable 160 Mb/s repeaterless transmission across 10 cm on-chip lines at figures of merit near 37 fJ/bit/mm .
Finally, the ElPho project integrates silicon photonics with MAPS via 3D stacking. Electro-absorption modulators, ring resonators, and WDM photonic fabrics target Tb/s throughput, optical power delivery, and near-sensor photonic preprocessing, paving the way for heterogeneous electro-photonic detectors .
Together, these advances illustrate a coherent roadmap: ultra-low-voltage front ends, dead-zone-free event-driven readout, repeaterless wafer-scale interconnects, and ultimately electro-photonic MAPS tailored for the extreme demands of the FCC-ee.
| Session | Sensors |
|---|
