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Description
The core electronics in the LHCb Calorimeter Detector are intended to measure the energy and time of arrival (ToA) of particles using two different ASICs (ICECAL65 and SPIDER, respectively). The expected radiation levels inside the detector have arisen the need to upgrade the design to a high-radiation resilient technology, such as TSMC65. This work presents the analog design of the ICECAL6, a 4-channel ASIC developed in a 65-nm CMOS technology for the continuous readout of Photomultiplier Tubes (PMTs).
The reduced voltage supply in this technology (1.2V) toughens up to achieve the required resolution of 12-bit resolution. Hence, a two-gain scheme has been adopted using a Low-Gain (LG) path with 11 bits of precision and a High-Gain (HG) path that increases this resolution by 1 additional bit against low-amplitude input signals. Following the design in the ICECAL ASIC already installed in the LHCb calorimeter, both paths are based on two time-interleaved subchannels that guarantee the continuous readout of the input samples arriving every 25 ns. This is accurately achieved by adding a Phase Locked Loop (PLL) that generates the necessary clocks for all the internal switched blocks individually per channel with a phase step configuration below 1 ns.
Each of these subchannels is based on a processing chain comprised of (1) a voltage preamplifier, (2) a configurable pole-zero cancellation circuit to mitigate the effect of the spillover generated by the different detector technologies (Shashlink, SPACAL-W, and SPACAL-Pb scintillators), (3) an integrator with tunable time constant τ, and (4) a high-slew-rate track-and-hold (T&H) based on the bottom plate sampling technique. All these blocks are built with a fully-differential rail-to-rail (RTR) amplifier with high-performance specifications which has been particularly designed for this ASIC with: (1) an equalized RTR input stage loaded with a folded cascode to achieve constant GBW along the whole common-mode (CM) input range (~ 500 MHz) and a high open-loop gain (Av0 ~ 85 dB); (2) a class-AB output to maintain the RTR swing at the output; (3) a common-mode feedback amplifier (CMFB) that ensures a minimum deviation from the CM output level. The analog processing chain is followed by an output buffer to cope with the pads' parasitics and the load of the external ADC in charge of digitizing the measurement.
Regarding the generation of the clocks inside the system, a PLL has been included to generate the 20 MHz integrator and T&H clocks individually per channel, and the 40 MHz clocks required by the external ADCs. It comprises a Phase and Frequency Detector (PFD), a charge pump followed by a loop filter, and a Voltage-Controlled Ring Oscillator (VCO) that generates a low-jitter clock of 1.28 GHz. This clock is processed by a digital clock manager to obtain the 20 MHz and 40 MHz required clocks.
The ICECAL65 ASIC has been already sent for manufacturing, and it is expected to be tested and verified in early 2026.
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