2–6 Dec 2025
Bologna, Italy
Europe/Rome timezone
Registration Deadline is ___ 19 November ___

A Digital SiPM for Photon Multiplicity Measurement operated with a Compact USB Readout

4 Dec 2025, 09:24
15m
Auditorium Enzo Biagi (Bologna, Italy)

Auditorium Enzo Biagi

Bologna, Italy

Talk Solid-State Photodetectors (eg. SPADs, traditional and digital SiPMs) Plenary Session

Speaker

Prof. Peter Fischer (Heidelberg University)

Description

We present a Digital SiPM sensor chip which measures photon multiplicities at a rate of $\gtrsim10\mathrm{\,MHz}$, which has been fabricated using the $350\mathrm{\,nm}$ technology of the Fraunhofer IMS (Duisburg, Germany). The demonstrator chip contains a matrix of $27\times24$ pixels with SPADs of $\approx2400\mathrm{\,mm}^2$ size. Photon hits in the SPADs occurring during an externally controlled accumulation time window are transferred to shift registers at the end of the interval. They are clocked out from the pixel matrix and counted digitally in the chip periphery while a new accumulation takes place. The digital counts are transferred off-chip serially with the possibility to daisy chain multiple chips, so that larger modules can be build with no increase in the number of required digital signals. A possible application of this chip is photon detection in the NEXT experiment which searches for neutrinoless double-beta decays.
A very compact USB interface has been developed to control and read out this and similar chips in test environments. A PCB of only $3\times 6\mathrm{\,cm}^2$ size contains a Hi-Speed USB interface, an FPGA and the programmable generation of two supply voltages and of the SPAD bias voltage, including current monitoring. All voltages are derived from the power delivered by the USB-C
connector, so that no further equipment is required. The Digital SiPM chip is connected to the interface via a single high speed flat cable containing 8 fast differential signals, 7 CMOS signals, 2 programmable supply voltages (for the chip and auxiliary circuity) and the SPAD bias. All digital signals can be programmed as output or input in the FPGA.
We will describe the chip architecture, the compact USB readout and present measurements taken with this setup.

Speaker Confirmation Yes

Author

Prof. Peter Fischer (Heidelberg University)

Co-authors

Mr Joris Witte (Heidelberg University) Dr Michael Keller (Heidelberg University)

Presentation materials

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