Introductory course to VHDL and HLS FPGA programming

Session

Introduction to VHDL

23 Jun 2025, 09:30

Università degli Studi Milano Bicocca

1. Introduction to FPGAs

Andrea Triossi (Universita` degli Studi di Padova)

23/06/2025, 09:30

3. FPGA design flow

Andrea Triossi (Universita` degli Studi di Padova)

23/06/2025, 10:00

Source files, Intellectual Property files, constraints files, Simulation, Synthesis, Implementation, Debugging

2. FPGA architecture

Andrea Triossi (Universita` degli Studi di Padova)

23/06/2025, 11:30

Overview of all the elements of an FPGA. Configurable logic blocks, Switch Matrix, I/O blocks, Look Up Tables, Storage elements, Memories, Shift registers, Multiplexers, Carry logic, Clock distribution, Clock buffers, Clock Management tile, FIFOs, Digital Signal Processors

5. Arithmetic operation in VHDL

Andrea Triossi (Universita` degli Studi di Padova)

Case study: the adder. Simulation of VHDL code through test bench

4. Combinatorial functions in VHDL

Andrea Triossi (Universita` degli Studi di Padova)

Basic examples of combinatorial functions in VHDL. VHDL types and type conversions