Speaker
Description
The LITE-SLPD (Lightweight Integrated Technology for Luminescence and Particle Detection) project explores the integration of advanced detection electronics within compact and low-power systems. As part of this effort, the GEN4 system introduces a fully integrated ASIC-based analog front-end for SiPM-based particle detection.
The ASIC chip, a key element of the GEN4 system, integrates core signal processing functionalities, including low-noise amplification, a fast discriminator, and a Peak & Hold circuit, previously implemented in discrete-component architectures. The front-end is designed using Second-Generation Current Conveyors (CCII+), optimized for reduced input impedance and enhanced recovery time, ensuring high-speed signal discrimination.
To support accurate circuit design and validation, a custom SiPM model has been developed in Cadence, reproducing realistic sensor behavior and facilitating front-end optimization. Simulations include transient response, AC analysis, and Monte Carlo evaluations of key circuit blocks, providing insight into performance variations across different conditions.
This talk will present the circuit architecture, highlighting key design choices such as the implementation of CCII+ structures with cascoded MOS stages, the biasing scheme and current-mode DAC, as well as the expected performance of the fast trigger generation and Peak & Hold response under increasing photon flux stimuli. Layout implementations and preliminary Monte Carlo results will also be discussed, outlining the next steps toward prototype realization.
