APE Router: an IP enabling low-latency packet communications for FPGA-based distributed processing.

6 Mar 2025, 09:45
25m
Aula Magna Lingotto (Torino)

Aula Magna Lingotto

Torino

Via Nizza 242, Torino

Speaker

Francesca Lo Cicero (Istituto Nazionale di Fisica Nucleare)

Description

The APE Router, developed by the INFN APE group, allows to implement a direct network for FPGA accelerators, enabling low-latency data transfer. This IP can be configured at design time for different environments, making it adaptable for applications ranging from embedded systems to large-scale HPC clusters and distributed FPGA-based systems.
Various applications will be presented, highlighting the APE Router’s ability to enable the development of scalable computing architectures.
A first use case is APEnet+, the high-performance low-latency interconnect system used in a hybrid CPU/GPU-based HPC platform.
The EURETILE project (EUropean REference TILed architecture Experiment) investigates and implements brain-inspired foundational innovations in the system architecture of massively parallel tiled computer architectures. In this project the APE Router, implemented in the DNP (Distributed Network Processor), manages all communication tasks, including deadlock-free routing, flow control, and integrity checks.
In the ExaNeSt project, focused on developing the interconnection network, storage, and cooling technologies required for exascale supercomputers, the APE Router aims to handle the communication between FPGAs in the basic compute node (QFDB) and between multiple QFDBs (intra-Mezzanine and inter-Mezzanine communications).
The EuroExa project, built on the results of ExaNeSt, aims to deliver an HPC platform using a modular integration approach to maximize cost-efficiency and scalability; the APE Router is used to connect computational nodes (CRDB) in a blade and to manage inter-blades connectivity.
Finally, the APE Router is the main component of the APEIRON framework, consisting of a generic architecture of an FPGA-based distributed stream processing system and the corresponding software stack.
One APEIRON application is partial particle identification on the stream of events generated by the RICH detector in the CERN NA62 experiment (FPGA RICH).
Additionally, APEIRON is used to implement a distributed ML model to discriminate between Noise Only and Signal + Noise events in the dRICH detector in the Epic experiment.

Primary author

Francesca Lo Cicero (Istituto Nazionale di Fisica Nucleare)

Presentation materials