Speaker
Description
Time-to-Digital Converters (TDCs) are key components in many physics experiments, particularly those requiring precise time measurements. In this work, we present an efficient and scalable TDC design embedded in an AMD Artix-7 Field Programmable Gate Array (FPGA). The TDC is tailored to meet the specific demands of high-performance physics experiments, operating with a resolution of 75ps and a measurement range of around 20 seconds. The TDC design leverages the inherent flexibility of FPGAs, enabling a highly adaptable solution that can easily be scaled. The design is implemented using only around 200 LUTs and 600 FlipFlops per channel. The architecture is based on four tapped delay lines, implemented using the CARRY4 components in the 7 series AMD FPGAs and a 32-bit coarse counter. The full-time measurement is built by Nutt’s interpolation. The TDC can measure the duration of a pulse or the interval between edges on two signals. The TDC is pipelined and runs at 200MHz. Each measurement takes a maximum of 12 clock cycles to complete. At the mentioned clock speed, this translates to a rate of 200MS/s.
Another key strength of this design is its ease of integration into existing FPGA-based systems. Since it requires minimal logic resources, it can be embedded alongside other signal processing components without significantly impacting the overall utilization of the FPGA. This makes it particularly suitable for multi-channel readout systems, where multiple TDC instances can be deployed in parallel. Furthermore, its low-latency architecture ensures that real-time applications can benefit from rapid and reliable time measurements.
To prove the portability of our design, we adapted it to an AMD Kintex Ultrascale+ FPGA, which runs our implementation a 400 MHz clock frequency and enhances the TDC least significant bit equivalent to 5ps. The faster hardware is expected to improve the resolution, throughput and latency of our TDC, making it an attractive option for even more demanding applications in experimental physics.
In conclusion, this FPGA-based TDC provides a resource-efficient, scalable, and high-performance solution for precision time measurements in physics experiments. Future developments will further enhance its capabilities, solidifying its role as a versatile tool for high-precision time measurement tasks. It is worth mentioning that this TDC design has potential uses in a wide range of other scientific and industrial domains and precise synchronization of distributed systems.
Keywords: Time-to-Digital Converter (TDC), FPGA, delay line
