Speaker
Description
NA64-e at CERN SPS is a missing energy search experiment looking for light dark matter particles production in the collision of a 100 GeV electron and positron (a part of POKER project) beams with an active thick target (electromagnetic calorimeter). The average beam intensity is approximately 5x106 particles per SPS spill of 4.8 s, resulting in an average particle rate of about 1 MHz. Looking forward to future higher intensity runs, the NA64 collaboration is currently working toward an upgrade of the DAQ system, introducing new front-end elements with faster response to cope with pile-up effects.
The new front-end elements will be integrated into the NA64 DAQ system through the UCF (Unified Communication Framework) serial protocol, nominally operating at 2.5 Gbps. This fast serial link encapsulates into its frames three independent “virtual” AXI-based communication: the data channel, the trigger and synchronization channel – based on the TCS (Trigger and Control System), and the slow-controls one, exploiting the IPBus framework. A key feature of the system is that, to ensure proper synchronization, the main clock for front-end elements is directly recovered from the fast serial link.
To read signals from the active target and from other PMT-based detectors, the “Waveboard” digitizer has been identified as the current leading option to replace the existing readout boards. This device is a 12-channels, 14-bits digitizer operating at 250 Ms/s, featuring a Kintex7-based Zynq7000 SoC, designed for a broad range of applications.
The scope of our work was implementing a FPGA firmware compatible with the NA64 DAQ system, foreseeing the UCF protocol as a back-end interface. The new firmware features a compatible data format and exploits the recovered clock as FPGA and FADC refence clock, with fully deterministic phase synchronization with the main TCS controller. The reference clock phase accuracy achieved is close to 300 ps which is the best value possible with the current NA64 DAQ configuration. In this contribution, I'll show the results of the “Waveboard” FPGA firmware development, challenges we faced and its integration status within the NA64 DAQ system, discussing in detail the performed R&D activities on the device firmware with focus on the synchronization part. I’ll also present some test results obtained in various setups.
