Speaker
Description
The growing demand for ever-larger datasets is a clear trend across nearly all areas of experimental physics. While computing power is essential for the processing farm responsible for handling these datasets, inefficient data movement can significantly undermine its effectiveness. Traditional networking stacks, responsible for managing network traffic, typically handle data via multiple copies, which results in expensive operations. A zero-copy networking approach can be achieved by integrating a remote direct memory access (RDMA) layer into the networking stack, offloading the processing workload to specialized hardware. FEROCE aims to enhance the conventional data acquisition system (DAQ) paradigm used in physics experiments by reducing the burden on back-end electronics. By adopting an efficient network protocol early in the data flow, the front-end electronics establish a direct link with the memory of DAQ computing nodes. Beyond the front-end, the entire DAQ system can be constructed solely from commercial off-the-shelf (COTS) hardware, leveraging the benefits of a widely adopted and well-established technology standard. FEROCE’s goal is to implement a lightweight version of the RoCEv2 stack on Field-Programmable Gate Array (FPGA), ensuring it is compatible with the size of the devices typically used in the front-end electronics of physics experiments. Additionally, it aims to include flash-based FPGA in the range of target devices, enabling deployment in radiation-intensive environments such as experimental halls in high-energy physics (HEP) experiments. The outcome of FEROCE is an FPGA core with a minimal resource footprint, capable of efficiently transmitting data buffers over a RoCEv2 network. The core has been designed to be as portable as possible, remaining vendor-agnostic for seamless integration into the front-end electronics of a wide variety of experiments. Its performance has been assessed within a network built on commodity hardware even in situations of traffic congestion.
