Speaker
Luigi Gaioni
(INFN Pavia)
Description
Six layers of microstrip detectors are foreseen in the present baseline design of the SuperB Silicon Vertex Tracker. Different strip pitches and lengths will be used in the various SVT layers; however, the capability of standing a high background rate and of operating with high hit detection efficiency will be a common feature of the innermost layers. These requirements set the need for a readout chip with analog channels with a short signal shaping time (25 to 100 ns in layers 0 – 3) to achieve an adequate time stamp resolution and a small pulse overlap. These channels are also required to provide a 4-bit hit amplitude resolution for dE/dx measurements. A new chip is being designed in a 130 nm CMOS process to comply with these specifications. This paper will discuss the solutions that are adopted in this chip for the various blocks of the analog channels, and will present the simulation results for the current design along with the expected performance in terms of parameters such as signal-to-noise ratio, dynamic range, linearity, power dissipation.
for the collaboration
on behalf of the SVT-SuperB Group
Primary author
Luigi Gaioni
(INFN Pavia)
