5–10 Feb 2012
INFN-LNF <!-- ID_UTENTE=503 -->
Europe/Rome timezone

TDC Readout Board v3

7 Feb 2012, 18:42
1m
<B>Aula B. Touschek, Bldg 36</B> (INFN-LNF <!-- ID_UTENTE=503 -->)

<B>Aula B. Touschek, Bldg 36</B>

INFN-LNF <!-- ID_UTENTE=503 -->

Via Enrico Fermi,40 Frascati
poster presentation New ideas Poster session

Speaker

Mr Grzegorz Korcyl (Jagiellonian University)

Description

Most of the physics experiments involving charged particle identification require precise time measurements. The rising requirements concerning the time resolution, the channel density, the accepted hit rate and finally the price per channel, force the development of new and versatile solutions which can be used in many applications. In order to meet these requirements, a Time to Digital Converter (TDC) module realized in FPGAs with integrated DAQ has been developed, produced and is currently under tests. High time resolution of less than 14 ps RMS and a high channel density (~256) allow to efficiently measure the time of flight of particles, being applicable for detectors like RPCs, scintillation counters with PMT readout or STTs. Together with the implemented network functionality, the module can serve as a standalone measurement device or a part of a larger system for of data acquisition. Optical links provide all the connectivity features needed in order to transfer data out to the event builders as well as for slow control purpose. Each link can be configured as a GbE link and connected directly to a standard Ethernet switch or as a generic serial link with a data rate up to 3.2 Gbps. One FPGA is responsible for collecting data from the 4 remaining FPGA-TDCs, sending it out and maintaining slow control channel over GbE network with a PC in control of the system. Basic network protocols have been implemented as FPGA logic, providing the “plug-and-play” functionality to the board, which after connecting to the network is able to receive IP address via DHCP, download configuration and be ready for measurements. The board is composed of 5x Lattice ECP3-150 FPGAs as compute power and 4x 208-pin connectors as well as 8x 3.2Gbps optical transceivers as IO interface. Its functionality can be additionally extended by connecting one AddOn-PCB or four Small AddOn-PCBs which can introduce different connection types or measurement devices. Its size is 20 cm times 23 cm and it is powered by a galvanically isolated 48V low noise power supply, predicted to consume around 30W electrical power at full speed operation.

Primary author

Mr Grzegorz Korcyl (Jagiellonian University)

Presentation materials