Speaker
Description
Starting from 2026, ALICE experiment at LHC is foreseeing an upgrade of the three innermost layers of the Inner Tracking System (ITS).
The new vertex detector will host three layers of wafer-scale truly cylindrical Monolithic Active Pixel Sensors realized in a 65 nm CMOS technology. The thinning down to less than 50 $\mu m$ in thickness will allow the bending silicon sensors to form a semi-cylindrical half layer without the need of stiff mechanical support structures. Thanks to this, an extremely low material budget (0.07 X/X$_0$ per layer) will be achieved, in combination with a reduction of the distance of the innermost layer from the beam axis. As a consequence, the tracking performance, especially at low transverse momenta ($\sim$ 0.1 GeV/c) will be improved.
The technology has been qualified with an extensive testing campaign on small scale structures realized in the MLR1 (Multi-Layer Reticle 1) submission. In particular, the results on radiation hardness and timing performance obtained with the Analogue Pixel Test Structure, not only demonstrated the suitability of the technology to the ITS upgrade requirements, but also showed its appeal for the next generation of collider experiments.
The presentation will report the ITS3 road-map to the realization of the first wafer-scale truly cylindrical vertex sensor. The latest results on the MLR1 test structures will be discussed with a particular focus on the analogue test structure equipped with fast individual operational amplifier-based buffering (APTS-OA). The detection efficiency of both analogue and digital test structures is higher than 99%, with a performance after the irradiation, Non-Ionizing Energy Loss of $10^{14}$ 1 MeV neutron equivalent cm$^{-2}$, well above the ALICE ITS3 requirements.
Moreover, the APTS-OA shows a time resolution as low as 63 ps, well below the one reached with the 180 nm CMOS process, paving the way for other applications in addition to the high energy physics.
