AMCHIP

Monday 27 Sept 2010, 09:30 → 18:00 Europe/Rome

09:30 → 10:00 Chip logic overview - plans for the future - costs - schedule

Speaker: P. Giannetti

Slides Overview_schedule_costs.ppt

10:00 → 10:30 Changes to be implemented into our 2D chip. Variable resolution patterns ....

Speaker: A. Annovi

Slides AMchip_changes_20100927.ppt

10:30 → 11:00 The 3D or 2,5D option

Speaker: P. Giannetti

Slides 3D.ppt

11:00 → 11:30 Standard Cell design - tools - details {block diagrams, routing, critical lines...}

Speaker: F. Crescioli

Slides amchip_stdcell.pdf amchip_stdcell.ppt

11:30 → 12:00 Full custum design - tools - selective precharge - cell timing

Speaker: M. Beretta

Slides CAM_custom_layer.ppt

12:00 → 13:00 break - lunch time

13:00 → 13:30 Simulation - test vectors - chip tests

Speaker: I. Sacco

Slides 3D.ppt

13:30 → 14:00 features necessary for LEVEL 1 apllication

Speaker: A. Shoening

14:00 → 14:30 DIscussion: questions and answers

Speaker: all

14:30 → 15:30 Funding agencies - other collaborators - EU applications...... - discussion

Speaker: P. Giannetti

Slides EU.ppt

15:30 → 16:30 free discussion

Speaker: all