Speaker
Description
Recent processors commonly used for HPC applications heavily rely on multi-threading and vectorization design to deliver high performance computing throughput. Exploiting these features efficiently in applications is not however an easy task, and several programming strategies have to be put in place to be able to exploit at best the computing performance. The aim of this talk is then to highlight the issues that programmers may encounter in programming recent processors, focusing on discussing the most relevant strategies and methodologies to program recent multi- and many-core architectures for lattice-based applications. Using codes based on Lattice Boltzmann Methods, the talk will present the major programming issues that are relevant to exploit a large fraction of available peak performance of the target processors, giving various programming solutions to get high efficiency of execution. The talk takes into account multi-core processors based on "traditional" core-architecture, as well as many-core systems such as GP-GPUs and Intel Xeon-Phi. It also considers several memory data-layouts to store the lattice domain, that meet the conflicting computing requirements of distinct parts of the application, and sustain a large fraction of peak performance both in terms of computing and memory throughput.
