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The aim of this work is to investigate the degradation induced by radiation on Dark Count Rate in a monolithic SPADs detector manufactured in a 150-nm CMOS process. This study has been done in order to check the suitability of CMOS SPADs for future applications requiring single-photon detection capability in radiation environments, like space or experiments at particle colliders.
For this purpose, an irradiation campaign has been carried out with protons and electrons to induce radiation damage effects on several test chips containing SPADs arrays with different geometries and implantation layouts.
The dark count rate has been measured as a function of the dose on a large amount of SPADs, showing that radiation-induced damage can be a serious issue for CMOS SPADs. Radiation can impact the device performance by creating interface traps of bulk defects responsible for the deterioration of the dark and noise performances of the detector.
We used the DCR analysis (specifically: its distribution, low frequency fluctuations, activation energy, annealing temperature) as a probe to study the basic mechanisms of radiation damage in silicon and the related induced defects.
Furthermore, we investigated cooling and thermal annealing, as possible methods of mitigation.
The obtained results have been investigated in the framework of several space mission case-studies. Expected radiation levels have been estimated by means of SPENVIS and considerations about the suitability of CMOS SPADS in space have been addressed.
