A 2-day training workshop on FPGA implementation of OpenCL is organized in the framework of the EU H2020 projects, EcoScale and ExaNeSt, collaboration.
The workshop aims to a) introduce people to the use of OpenCL, b) discuss the differences between optimizing OpenCL code for GPU or FPGA and c) provide methods to obtain an RTL with the best performance.
Few general presentations and hand-on sessions on OpenCL development flow and related tools are foreseen. We will mostly focus on Vivado HLS, the tool where the performance, architecture and power optimization takes place. We will also have a brief look at SDAccel or SDx, the tools that "glue" together the C/C++ host code with the kernels running on the FPGA, both in terms of performance analysis and in terms of driver code generation.
