Submission of a prototype chip with analog channels for L4-5

• Bayan Nasri (MI)

Update on analog design for fast channels L0-L3 and peripheral blocks

• Valerio Re (PV)

Update on in-strip logic design

• Roberto Beccherle (GE)

Update on readout architecture VHDL simulation

• Filippo Maria Giorgi (BO)

Discussion